[all-commits] [llvm/llvm-project] 3bdaf2: VirtRegRewriter: Add super register defs for live ...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/issue98474-register-coalescer-verifier-error
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bdaf207671d668757559b8c38f1045e54a79cc8
      https://github.com/llvm/llvm-project/commit/3bdaf207671d668757559b8c38f1045e54a79cc8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-10-25 (Fri, 25 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/VirtRegMap.cpp
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
    A llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll
    A llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
    M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
    A llvm/test/MachineVerifier/AMDGPU/issue98474-missing-def-liveout-physical-subregister.mir

  Log Message:
  -----------
  VirtRegRewriter: Add super register defs for live out undef lanes

If an undef subregister def is live into another block, we need to
maintain a physreg def to track the liveness of those lanes. This
would manifest a verifier error after branch folding, when the cloned
tail block use no longer had a def.

There is a missing verifier check for this situation. Added an xfailed
test that demonstrates this. We may also be able to revert the changes
in 47d3cbcf842a036c20c3f1c74255cdfc213f41c2.

It might be better to insert an IMPLICIT_DEF before the instruction
rather than using the implicit-def operand.

Fixes #98474


  Commit: 41d4717f59afbf7744927d38102e07e7c6f1f578
      https://github.com/llvm/llvm-project/commit/41d4717f59afbf7744927d38102e07e7c6f1f578
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-10-25 (Fri, 25 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/VirtRegMap.cpp

  Log Message:
  -----------
  Try to fix clobbering lanes in other assigned lanes of physreg


  Commit: f80bb2913b02aa1921e37a04717acfccbfa39ba8
      https://github.com/llvm/llvm-project/commit/f80bb2913b02aa1921e37a04717acfccbfa39ba8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-10-25 (Fri, 25 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/LiveRegMatrix.h
    M llvm/lib/CodeGen/LiveRegMatrix.cpp
    M llvm/lib/CodeGen/VirtRegMap.cpp
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
    A llvm/test/CodeGen/AMDGPU/issue98474-assigned-physreg-interference.mir
    M llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir
    M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll

  Log Message:
  -----------
  Use LiveRegMatrix and only add necessary impdefs

We apparently need to detect interference with other assigned
intervals to avoid clobbering the undef lanes defined in other
intervals, since the undef def didn't count as interference.

This is pretty ugly and adds a new dependency on LiveRegMatrix,
keeping it live for one more pass. It also adds a lot of implicit
operand spam (we really should have a better representation for this).


  Commit: 4456624cc6ec42f95cd3e16939f62f51e3d9a20c
      https://github.com/llvm/llvm-project/commit/4456624cc6ec42f95cd3e16939f62f51e3d9a20c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-10-25 (Fri, 25 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/VirtRegMap.cpp

  Log Message:
  -----------
  More comments


Compare: https://github.com/llvm/llvm-project/compare/b0b1659a7005...4456624cc6ec

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