[all-commits] [llvm/llvm-project] a0c318: [CodeGen][NFC] Properly split MachineLICM and Earl...

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a0c318938a528cfbef509a2516b36dd2411a52b6
      https://github.com/llvm/llvm-project/commit/a0c318938a528cfbef509a2516b36dd2411a52b6
  Author: Gaëtan Bossu <41161573+gbossu at users.noreply.github.com>
  Date:   2024-10-25 (Fri, 25 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineLICM.cpp
    M llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
    M llvm/test/CodeGen/AMDGPU/licm-regpressure.mir
    M llvm/test/CodeGen/AMDGPU/licm-valu.mir
    M llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
    M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir

  Log Message:
  -----------
  [CodeGen][NFC] Properly split MachineLICM and EarlyMachineLICM (#113573)

Both are based on MachineLICMBase, and the functionality there is
"switched" based on a PreRegAlloc flag. This commit is simply about
trusting the original value of that flag, defined by the `MachineLICM`
and `EarlyMachineLICM` classes.

The `PreRegAlloc` flag used to be overwritten it based on MRI.isSSA(),
which is un-reliable due to how it is inferred by the MIRParser. I see
that we can now define isSSA in MIR (thanks @gargaroff ), meaning the
fix isn’t really needed anymore, but redefining that flag still feels
wrong.

Note that I'm looking into upstreaming more changes to MachineLICM, see
[the discourse
thread](https://discourse.llvm.org/t/extending-post-regalloc-machinelicm/82725).



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