[all-commits] [llvm/llvm-project] 403e4a: [AArch64] Add assembly/disassembly for SVE zeroing...

[SpencerAbson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 403e4a2074910fcec139a8fbb77f3c2d15643916
      https://github.com/llvm/llvm-project/commit/403e4a2074910fcec139a8fbb77f3c2d15643916
  Author: SpencerAbson <Spencer.Abson at arm.com>
  Date:   2024-10-25 (Fri, 25 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p2/fcvtzs_z-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p2/fcvtzs_z.s
    A llvm/test/MC/AArch64/SVE2p2/fcvtzu_z-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p2/fcvtzu_z.s
    A llvm/test/MC/AArch64/SVE2p2/flogb_z-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p2/flogb_z.s
    A llvm/test/MC/AArch64/SVE2p2/scvtf_z-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p2/scvtf_z.s
    A llvm/test/MC/AArch64/SVE2p2/ucvtf_z-diagnostics.s
    A llvm/test/MC/AArch64/SVE2p2/ucvtf_z.s

  Log Message:
  -----------
  [AArch64] Add assembly/disassembly for SVE zeroing int-float conversions (#113605)

This patch adds assembly/disassembly for the following predicated SVE2.2
instructions

    - SCVTF (zeroing)
    - UCVTF (zeroing)
    - FCVTZS (zeroing)
    - FCVTZU (zeroing)
    - FLOGB (zeroing)
- In accordance with:
https://developer.arm.com/documentation/ddi0602/latest/



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