[all-commits] [llvm/llvm-project] c03d09: [aarch64] atan2 intrinsic lowering (p5) (#112611)
Alexander Richardson via All-commits
all-commits at lists.llvm.org
Thu Oct 24 18:19:51 PDT 2024
Branch: refs/heads/users/arichardson/spr/datalayout-refactor-storage-of-non-integral-address-spaces
Home: https://github.com/llvm/llvm-project
Commit: c03d09ce3eed336fea4d9283232383f6d4d4057d
https://github.com/llvm/llvm-project/commit/c03d09ce3eed336fea4d9283232383f6d4d4057d
Author: Tex Riddell <texr at microsoft.com>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-atan2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics.ll
M llvm/test/CodeGen/AArch64/illegal-float-ops.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-calls-libsystem-darwin.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
Log Message:
-----------
[aarch64] atan2 intrinsic lowering (p5) (#112611)
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
- `VecFuncs.def`: define intrinsic to sleef/armpl mapping
- `LegalizerHelper.cpp`: add missing fewerElementsVector handling for
the new atan2 intrinsic
- `AArch64ISelLowering.cpp`: Add arch64 specializations for lowering
like neon instructions
- `AArch64LegalizerInfo.cpp`: Legalize atan2.
Part 5 for Implement the atan2 HLSL Function #70096.
Commit: c4248fa3edd3e2e18219b4fb46561ca1bfd65728
https://github.com/llvm/llvm-project/commit/c4248fa3edd3e2e18219b4fb46561ca1bfd65728
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-10-25 (Fri, 25 Oct 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/immintrin.h
A clang/lib/Headers/movrs_avx10_2_512intrin.h
A clang/lib/Headers/movrs_avx10_2intrin.h
A clang/test/CodeGen/X86/movrs-avx10.2-512-builtins-error-32.c
A clang/test/CodeGen/X86/movrs-avx10.2-512-builtins.c
A clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c
A clang/test/CodeGen/X86/movrs-avx10.2-builtins.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll
A llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll
A llvm/test/MC/Disassembler/X86/movrs-avx10-64.txt
A llvm/test/MC/X86/movrs-avx10-att-64.s
A llvm/test/MC/X86/movrs-avx10-intel-64.s
Log Message:
-----------
[X86] Support MOVRS and AVX10.2 instructions. (#113274)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
Commit: 08159e6e117f5717d30230cb6568d7f3686b2c86
https://github.com/llvm/llvm-project/commit/08159e6e117f5717d30230cb6568d7f3686b2c86
Author: A. Jiang <de34 at live.cn>
Date: 2024-10-25 (Fri, 25 Oct 2024)
Changed paths:
M libcxx/include/__charconv/from_chars_floating_point.h
M libcxx/include/__config
M libcxx/src/charconv.cpp
Log Message:
-----------
[libc++] __uglify `[[clang::noescape]]` (#113280)
Identifiers `clang` and `noescape` are not reserved by the C++ standard,
so perhaps we need to use the equivalent reserved forms.
Also changes the occurrences of that attribute to a macro, following the
convention for `[[_Clang::__lifetimebound__]]`.
Addresses
https://github.com/llvm/llvm-project/pull/91651#discussion_r1807852646.
Commit: c9b10a94b56411ba3b7cc3a148edb257b7e88fcd
https://github.com/llvm/llvm-project/commit/c9b10a94b56411ba3b7cc3a148edb257b7e88fcd
Author: William Junda Huang <williamjhuang at google.com>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M llvm/lib/Linker/IRMover.cpp
A llvm/test/ThinLTO/X86/Inputs/ditemplatevalueparameter-remap.ll
A llvm/test/ThinLTO/X86/ditemplatevalueparameter-remap.ll
Log Message:
-----------
[ThinLTO] Do not duplicate import a function that is actually defined in the current module #110064 (#111933)
Trying to land #110064 again after fixing test case
Commit: a35ebcf255046bc78ea86b3c524e0836425a1156
https://github.com/llvm/llvm-project/commit/a35ebcf255046bc78ea86b3c524e0836425a1156
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M lld/test/wasm/lto/Inputs/archive.ll
M lld/test/wasm/lto/Inputs/cache.ll
M lld/test/wasm/lto/Inputs/comdat_ordering1.ll
M lld/test/wasm/lto/Inputs/comdat_ordering2.ll
M lld/test/wasm/lto/Inputs/foo.ll
M lld/test/wasm/lto/Inputs/libcall-archive.ll
M lld/test/wasm/lto/Inputs/libcall-truncsfhf2.ll
M lld/test/wasm/lto/Inputs/libcall.ll
M lld/test/wasm/lto/Inputs/save-temps.ll
M lld/test/wasm/lto/Inputs/thin1.ll
M lld/test/wasm/lto/Inputs/thin2.ll
M lld/test/wasm/lto/Inputs/thinlto.ll
M lld/test/wasm/lto/Inputs/used.ll
M lld/test/wasm/lto/archive.ll
M lld/test/wasm/lto/atomics.ll
M lld/test/wasm/lto/cache-warnings.ll
M lld/test/wasm/lto/cache.ll
M lld/test/wasm/lto/cgo.ll
M lld/test/wasm/lto/comdat.ll
M lld/test/wasm/lto/diagnostics.ll
M lld/test/wasm/lto/export.ll
M lld/test/wasm/lto/import-attributes.ll
M lld/test/wasm/lto/internalize-basic.ll
M lld/test/wasm/lto/libcall-archive.ll
M lld/test/wasm/lto/libcall-truncsfhf2.ll
M lld/test/wasm/lto/lto-start.ll
M lld/test/wasm/lto/new-pass-manager.ll
M lld/test/wasm/lto/opt-level.ll
M lld/test/wasm/lto/parallel.ll
M lld/test/wasm/lto/relocatable-undefined.ll
M lld/test/wasm/lto/relocatable.ll
M lld/test/wasm/lto/save-temps.ll
M lld/test/wasm/lto/thin-archivecollision.ll
M lld/test/wasm/lto/thinlto-thin-archive-collision.ll
M lld/test/wasm/lto/thinlto.ll
M lld/test/wasm/lto/undef.ll
M lld/test/wasm/lto/used.ll
M lld/test/wasm/lto/verify-invalid.ll
M lld/test/wasm/lto/weak-undefined.ll
M lld/test/wasm/lto/weak.ll
Log Message:
-----------
[lld][WebAssembly] Update datalayout strings to latest version
These mismatched data layouts are exposed by the refactoring in
https://github.com/llvm/llvm-project/pull/105734 that now also
compares the non-integral pointers list of the data layout.
I dropped the explicit definition from all tests that use opt/llc since
those tools will insert the correct value, but for the llvm-as based
tests and explicit layout is required.
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/107276
Commit: 4bd52099c2b3c4635ec7009bdbf9d0012420f6b6
https://github.com/llvm/llvm-project/commit/4bd52099c2b3c4635ec7009bdbf9d0012420f6b6
Author: Alex Richardson <alexrichardson at google.com>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/include/clang/Driver/Options.td
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/immintrin.h
A clang/lib/Headers/movrs_avx10_2_512intrin.h
A clang/lib/Headers/movrs_avx10_2intrin.h
A clang/test/CodeGen/X86/movrs-avx10.2-512-builtins-error-32.c
A clang/test/CodeGen/X86/movrs-avx10.2-512-builtins.c
A clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c
A clang/test/CodeGen/X86/movrs-avx10.2-builtins.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M libcxx/include/__charconv/from_chars_floating_point.h
M libcxx/include/__config
M libcxx/src/charconv.cpp
M lld/test/wasm/lto/Inputs/archive.ll
M lld/test/wasm/lto/Inputs/cache.ll
M lld/test/wasm/lto/Inputs/comdat_ordering1.ll
M lld/test/wasm/lto/Inputs/comdat_ordering2.ll
M lld/test/wasm/lto/Inputs/foo.ll
M lld/test/wasm/lto/Inputs/libcall-archive.ll
M lld/test/wasm/lto/Inputs/libcall-truncsfhf2.ll
M lld/test/wasm/lto/Inputs/libcall.ll
M lld/test/wasm/lto/Inputs/save-temps.ll
M lld/test/wasm/lto/Inputs/thin1.ll
M lld/test/wasm/lto/Inputs/thin2.ll
M lld/test/wasm/lto/Inputs/thinlto.ll
M lld/test/wasm/lto/Inputs/used.ll
M lld/test/wasm/lto/archive.ll
M lld/test/wasm/lto/atomics.ll
M lld/test/wasm/lto/cache-warnings.ll
M lld/test/wasm/lto/cache.ll
M lld/test/wasm/lto/cgo.ll
M lld/test/wasm/lto/comdat.ll
M lld/test/wasm/lto/diagnostics.ll
M lld/test/wasm/lto/export.ll
M lld/test/wasm/lto/import-attributes.ll
M lld/test/wasm/lto/internalize-basic.ll
M lld/test/wasm/lto/libcall-archive.ll
M lld/test/wasm/lto/libcall-truncsfhf2.ll
M lld/test/wasm/lto/lto-start.ll
M lld/test/wasm/lto/new-pass-manager.ll
M lld/test/wasm/lto/opt-level.ll
M lld/test/wasm/lto/parallel.ll
M lld/test/wasm/lto/relocatable-undefined.ll
M lld/test/wasm/lto/relocatable.ll
M lld/test/wasm/lto/save-temps.ll
M lld/test/wasm/lto/thin-archivecollision.ll
M lld/test/wasm/lto/thinlto-thin-archive-collision.ll
M lld/test/wasm/lto/thinlto.ll
M lld/test/wasm/lto/undef.ll
M lld/test/wasm/lto/used.ll
M lld/test/wasm/lto/verify-invalid.ll
M lld/test/wasm/lto/weak-undefined.ll
M lld/test/wasm/lto/weak.ll
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/IR/DataLayout.h
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/IR/DataLayout.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-atan2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics.ll
M llvm/test/CodeGen/AArch64/illegal-float-ops.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
A llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll
A llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll
A llvm/test/MC/Disassembler/X86/movrs-avx10-64.txt
A llvm/test/MC/X86/movrs-avx10-att-64.s
A llvm/test/MC/X86/movrs-avx10-intel-64.s
A llvm/test/ThinLTO/X86/Inputs/ditemplatevalueparameter-remap.ll
A llvm/test/ThinLTO/X86/ditemplatevalueparameter-remap.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-calls-libsystem-darwin.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
Log Message:
-----------
address feedback
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/1bda0dd2b3bd...4bd52099c2b3
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