[all-commits] [llvm/llvm-project] 401d12: [MCP] Optimize copies when src is used during back...

[Vladimir Radosavljevic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 401d123a1fdcbbf4ae7a20178957b7e3a625c044
      https://github.com/llvm/llvm-project/commit/401d123a1fdcbbf4ae7a20178957b7e3a625c044
  Author: Vladimir Radosavljevic <129192835+vladimirradosavljevic at users.noreply.github.com>
  Date:   2024-10-23 (Wed, 23 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineCopyPropagation.cpp
    A llvm/test/CodeGen/AArch64/machine-cp-backward-uses.mir
    M llvm/test/CodeGen/ARM/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
    M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
    M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
    M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
    M llvm/test/CodeGen/Mips/mcount.ll
    M llvm/test/CodeGen/Mips/micromips-gp-rc.ll
    M llvm/test/CodeGen/Mips/tailcall/tailcall.ll
    M llvm/test/CodeGen/Mips/tls.ll
    M llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
    M llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
    M llvm/test/CodeGen/X86/matrix-multiply.ll
    M llvm/test/CodeGen/X86/midpoint-int.ll
    M llvm/test/CodeGen/X86/mul-i1024.ll
    M llvm/test/CodeGen/X86/mul-i512.ll
    M llvm/test/CodeGen/X86/pr46877.ll
    M llvm/test/CodeGen/X86/sdiv_fix.ll
    M llvm/test/CodeGen/X86/shift-and.ll
    M llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/X86/sqrt-fastmath.ll
    M llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/X86/vec_smulo.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
    M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll

  Log Message:
  -----------
  [MCP] Optimize copies when src is used during backward propagation (#111130)

Before this patch, redundant COPY couldn't be removed for the following
case:
```
  $R0 = OP ...
  ... // Read of %R0
  $R1 = COPY killed $R0
```
This patch adds support for tracking the users of the source register
during backward propagation, so that we can remove the redundant COPY in
the above case and optimize it to:
```
  $R1 = OP ...
  ... // Replace all uses of %R0 with $R1
```



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