[all-commits] [llvm/llvm-project] f58ce1: [NFC][TableGen] Use auto when initializing variabl...

Mon Oct 21 13:16:07 PDT 2024

  Branch: refs/heads/users/vitalybuka/spr/main.msan-reduces-overhead-of-todo-by-10
  Home:   https://github.com/llvm/llvm-project
  Commit: f58ce1152703ca753794b8cef36da30bd2668d0f
      https://github.com/llvm/llvm-project/commit/f58ce1152703ca753794b8cef36da30bd2668d0f
  Author: Rahul Joshi <rjoshi at nvidia.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M llvm/include/llvm/TableGen/Record.h
    M llvm/lib/TableGen/Record.cpp
    M llvm/lib/TableGen/SetTheory.cpp
    M llvm/lib/TableGen/TGParser.cpp

  Log Message:
  -----------
  [NFC][TableGen] Use auto when initializing variables with cast<> (#113171)

Use `auto` when initializing a variable with `cast<>`. Remove some
unneeded `const_cast` (since all Init pointers are now const).

  Commit: e6ada7162e25ab28f6e588fba23f0c11dd1238b5
      https://github.com/llvm/llvm-project/commit/e6ada7162e25ab28f6e588fba23f0c11dd1238b5
  Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/CalcSpillWeights.h
    M llvm/include/llvm/CodeGen/LiveIntervals.h
    M llvm/lib/CodeGen/CalcSpillWeights.cpp
    M llvm/lib/CodeGen/LiveIntervals.cpp
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    A llvm/test/CodeGen/AArch64/regalloc-spill-weight-basic.ll

  Log Message:
  -----------
  [regalloc][basic] Change spill weight for optsize funcs (#112960)

Change the spill weight calculations for `optsize` functions to remove
the block frequency multiplier. For those functions, we do not want to
consider the runtime cost of spilling, only the codesize cost.

I built a large app with the basic and greedy (default) register
allocator enabled.

| Regalloc Type | Uncompressed Size Delta | Compressed Size Delta |
| - | - | - |
| Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) |
| Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) |

Since I only saw a size win with the basic register allocator, I decided
to only change the behavior for that type.

  Commit: 40ea92c859234d536553cf26650e89d6e52071c6
      https://github.com/llvm/llvm-project/commit/40ea92c859234d536553cf26650e89d6e52071c6
  Author: Jonas Devlieghere <jonas at devlieghere.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M lldb/unittests/ScriptInterpreter/Lua/ScriptInterpreterTests.cpp

  Log Message:
  -----------
  [lldb] Update ScriptInterpreterTests for CommandReturnObject API change

  Commit: 622e398d8828431e082a336814d29932e22c8450
      https://github.com/llvm/llvm-project/commit/622e398d8828431e082a336814d29932e22c8450
  Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsAMDGPU.def
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Sema/SemaAMDGPU.cpp
    M clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
    M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx9.cl

  Log Message:
  -----------
  [AMDGPU] Allow overload of __builtin_amdgcn_mov/update_dpp (#112447)

We need to support 64-bit data types (intrinsics do support it). We are
also silently converting FP to integer argument now, also fixed.

  Commit: 4b1b51ac52445f2308174287c721ad7f60a8053b
      https://github.com/llvm/llvm-project/commit/4b1b51ac52445f2308174287c721ad7f60a8053b
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
    M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
    M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll

  Log Message:
  -----------
  [SLP]Initial non-power-of-2 support (but still whole register) for reductions

Enables initial non-power-of-2 support (but still requires number of
elements, forming whole registers) for reductions.
Enables extra vectorization for
MultiSource/Benchmarks/7zip/7zip-benchmark, CINT2006/464.h264ref and
CFP2017rate/526.blender_r (checked for SSE2)

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/112361

  Commit: dca43a1c82f1023127343daae487c3a6a8c7e3d4
      https://github.com/llvm/llvm-project/commit/dca43a1c82f1023127343daae487c3a6a8c7e3d4
  Author: Arthur Eubanks <aeubanks at google.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M lld/test/MachO/objc-category-merging-minimal.s

  Log Message:
  -----------
  [lld/Macho][test] Mark objc-category-merging-minimal.s as unsupported on Windows (#113209)

With #112981, the test uses awk, which gnuwin32 doesn't seem to have.

  Commit: 009fb567ceb9a8afea3c13b5eb943a1f15fdf3b5
      https://github.com/llvm/llvm-project/commit/009fb567ceb9a8afea3c13b5eb943a1f15fdf3b5
  Author: David Green <david.green at arm.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/rqshrn.ll

  Log Message:
  -----------
  [AArch64] Add patterns for combining qxtn+rshr to qrshrn

Similar to bd861d0e690cfd05184d86, this adds some patterns for converting
signed and unsigned variants of rshr+qxtn to qrshrn.

  Commit: 66ed5ed63c94238fded43063cd803c4340ac9d07
      https://github.com/llvm/llvm-project/commit/66ed5ed63c94238fded43063cd803c4340ac9d07
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsAMDGPU.def
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Sema/SemaAMDGPU.cpp
    M clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
    M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx9.cl
    M lld/test/MachO/objc-category-merging-minimal.s
    M lldb/unittests/ScriptInterpreter/Lua/ScriptInterpreterTests.cpp
    M llvm/include/llvm/CodeGen/CalcSpillWeights.h
    M llvm/include/llvm/CodeGen/LiveIntervals.h
    M llvm/include/llvm/TableGen/Record.h
    M llvm/lib/CodeGen/CalcSpillWeights.cpp
    M llvm/lib/CodeGen/LiveIntervals.cpp
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    M llvm/lib/TableGen/Record.cpp
    M llvm/lib/TableGen/SetTheory.cpp
    M llvm/lib/TableGen/TGParser.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    A llvm/test/CodeGen/AArch64/regalloc-spill-weight-basic.ll
    A llvm/test/CodeGen/AArch64/rqshrn.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
    M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
    M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

Compare: https://github.com/llvm/llvm-project/compare/3e7ec5b11042...66ed5ed63c94

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