[all-commits] [llvm/llvm-project] ecfeac: [AArch64] Convert aarch64_neon_sqxtn to ISD::TRUNC...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Mon Oct 21 11:47:42 PDT 2024
Branch: refs/heads/users/kparzysz/spr/i01-flang-iterator-modifier
Home: https://github.com/llvm/llvm-project
Commit: ecfeacd152f07cf8aea210f63415e3e48b05ab22
https://github.com/llvm/llvm-project/commit/ecfeacd152f07cf8aea210f63415e3e48b05ab22
Author: David Green <david.green at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] Convert aarch64_neon_sqxtn to ISD::TRUNCATE_SSAT_S and replace tablegen patterns
This lowers the aarch64_neon_sqxtn intrinsics to the new TRUNCATE_SSAT_S ISD
nodes, performing the same for sqxtun and uqxtn. This allows us to clean up the
tablegen patterns a little and in a future commit add combines for sqxtn.
Commit: c44860c8d2582abd88794267b4fa0fa953bbef80
https://github.com/llvm/llvm-project/commit/c44860c8d2582abd88794267b4fa0fa953bbef80
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[Flang][OpenMP] Disable lowering of omp.simd reductions in composites (#112686)
Currently, the `omp.simd` operation is ignored during MLIR to LLVM IR
translation when it takes part in a composite construct. One consequence
of this limitation is that any entry block arguments defined by that
operation will trigger a compiler crash if they are used anywhere, as
they are not bound to an LLVM IR value.
A previous PR introducing support for the `reduction` clause resulted in
the creation and use of entry block arguments attached to the `omp.simd`
operation, causing compiler crashes on 'do simd reduction(...)'
constructs.
This patch disables Flang lowering of simd reductions in 'do simd'
constructs to avoid triggering these errors while translation to LLVM IR
is still incomplete.
Commit: 5c9c281c251402fd65bb01717112cf22019ee409
https://github.com/llvm/llvm-project/commit/5c9c281c251402fd65bb01717112cf22019ee409
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h
M llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
Log Message:
-----------
[DebugInfo] Use heterogenous lookups with std::map (NFC) (#113118)
Commit: 61a286ac0817671ad09a505303b7a3a446798316
https://github.com/llvm/llvm-project/commit/61a286ac0817671ad09a505303b7a3a446798316
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
Log Message:
-----------
[tools] Don't call StringRef::str() when calling StringMap::find (NFC) (#113119)
StringMap::find takes StringRef. We don't need to create an instance
of std::string from StringRef only to convert it right back to
StringRef.
Commit: 1bf1e92c72ec9086ab24103cf968e115b7248101
https://github.com/llvm/llvm-project/commit/1bf1e92c72ec9086ab24103cf968e115b7248101
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
Log Message:
-----------
[lldb] Avoid repeated map lookups (NFC) (#113121)
Commit: af6e1881e0791ac1ee611b62a3d12d9fb03ca142
https://github.com/llvm/llvm-project/commit/af6e1881e0791ac1ee611b62a3d12d9fb03ca142
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
Log Message:
-----------
[mlir] Avoid repeated map lookups (NFC) (#113122)
Commit: e2074c60bb3982cd8afb6408670332ea27da6383
https://github.com/llvm/llvm-project/commit/e2074c60bb3982cd8afb6408670332ea27da6383
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
Log Message:
-----------
[AArch64] Use implicitTrunc in isBitfieldDstMask() (NFC)
This code intentionally discards the high bits, so set
implicitTrunc=true. This is currently NFC but will enable an
APInt assertion in the future.
Commit: f0312d962d0510d613a5ad1aec0f0e44d4f124c0
https://github.com/llvm/llvm-project/commit/f0312d962d0510d613a5ad1aec0f0e44d4f124c0
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/test/lib/Pass/CMakeLists.txt
A mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/mlir-spirv-cpu-runner/double.mlir
M mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
Log Message:
-----------
[mlir][mlir-spirv-cpu-runner] Move MLIR pass pipeline to mlir-opt (#111575)
Adds a new mlir-opt test-only pass, -test-spirv-cpu-runner-pipeline,
which runs the set of MLIR passes needed for the mlir-spirv-cpu-runner,
and removes them from the runner. The tests are changed to invoke
mlir-opt with this flag before running the runner. The eventual goal is
to move all host/device code generation steps out of the runner, like
with some of the other runners.
Commit: f2302ed3d0f84ca867a3e664ed65bc89e52ee670
https://github.com/llvm/llvm-project/commit/f2302ed3d0f84ca867a3e664ed65bc89e52ee670
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
Log Message:
-----------
[RISCV][GISEL] Fix operand on RISCV::G_VMV_V_V_VL
6bac41496eb24c80aa659008d08220355a617c49 added this opcode with the wrong
number of operands. It didn't fail on check-llvm for me or on pre-commit CI,
but once committed we got buildbot failures. This patch fixes the definition
of the instruction and fixes the failing test.
Commit: bd861d0e690cfd05184d86e954289cccfec97e92
https://github.com/llvm/llvm-project/commit/bd861d0e690cfd05184d86e954289cccfec97e92
Author: David Green <david.green at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/qshrn.ll
Log Message:
-----------
[AArch64] Add some basic patterns for qshrn.
With the truncssat nodes these are relatively simple tablegen patterns to add.
The existing intrinsics are converted to shift+truncsat to they can lower using
the new patterns.
Fixes #112925.
Commit: 1dfdbf716112627dea5e79f7f4f1e1e9335ee9df
https://github.com/llvm/llvm-project/commit/1dfdbf716112627dea5e79f7f4f1e1e9335ee9df
Author: Boaz Brickner <brickner at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/test/CXX/drs/cwg9xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add covariance tests that make sure we return an error when return value is different in pointer / lvalue ref / rvalue ref (#112853)
Per https://cplusplus.github.io/CWG/issues/960.html.
Commit: 67ff5ba9af9754261abe11d762af11532a816126
https://github.com/llvm/llvm-project/commit/67ff5ba9af9754261abe11d762af11532a816126
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/MC/AArch64/LSFE/directive-arch-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension.s
A llvm/test/MC/AArch64/LSFE/directive-cpu-negative.s
A llvm/test/MC/AArch64/LSFE/directive-cpu.s
A llvm/test/MC/AArch64/LSFE/ldfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfadd.s
A llvm/test/MC/AArch64/LSFE/ldfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmax.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm.s
A llvm/test/MC/AArch64/LSFE/ldfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmin.s
A llvm/test/MC/AArch64/LSFE/ldfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfminnm.s
A llvm/test/MC/AArch64/LSFE/stfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfadd.s
A llvm/test/MC/AArch64/LSFE/stfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmax.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm.s
A llvm/test/MC/AArch64/LSFE/stfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmin.s
A llvm/test/MC/AArch64/LSFE/stfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfminnm.s
Log Message:
-----------
[AArch64] Add assembly/disaasembly of atomic ld/st (#112892)
This patch adds assembly/disassembly for the following instructions:
ldfadd{a,al,l,}, ldbfadd{a,al,l,}
ldfmax{a,al,l,}, ldbfmax{a,al,l,}
ldfmaxnm{a,al,l,}, ldbfmaxnm{a,al,l,}
ldfmin{a,al,l,}, ldbfmin{a,al,l,}
ldfminnm{a,al,l,} ldbfminnm{a,al,l,}
stfadd{l,}, stbfadd{l,}
stfmax{l,}, stbfmax{l,}
stfmaxnm{l,}, stbfmaxnm{l,}
stfmin{l,}, stbfmin{l,}
stfminnm{l,}, stbfminnm{l,}
According to [1]
[1]https://developer.arm.com/documentation/ddi0602
Co-authored-by: Spencer Abson
[spencer.abson at arm.com](mailto:spencer.abson at arm.com)
Co-authored-by: Caroline Concatto
[caroline.concatto at arm.com](mailto:caroline.concatto at arm.com)
Commit: a2ba438f3e5635e368333213914c7452a6a6a2da
https://github.com/llvm/llvm-project/commit/a2ba438f3e5635e368333213914c7452a6a6a2da
Author: XChy <xxs_chy at outlook.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
Log Message:
-----------
[InstCombine] Preserve the flag from RHS only if the `and` is bitwise (#113164)
Fixes #113123
Alive proof: https://alive2.llvm.org/ce/z/hnqeLC
Commit: 1e07c4800cf46ac9e4748b664cb58cbd48acb918
https://github.com/llvm/llvm-project/commit/1e07c4800cf46ac9e4748b664cb58cbd48acb918
Author: Chris Apple <cja-private at pm.me>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M compiler-rt/lib/rtsan/CMakeLists.txt
R compiler-rt/lib/rtsan/rtsan_interceptors.cpp
A compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
R compiler-rt/lib/rtsan/tests/rtsan_test_interceptors.cpp
A compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[rtsan][NFC] Rename *interceptors.cpp to *interceptors_posix.cpp (#112935)
Done in preparation of exploring rtsan on windows.
Commit: 4679583181a9032b4f7c6476c7a1bfefe5724b47
https://github.com/llvm/llvm-project/commit/4679583181a9032b4f7c6476c7a1bfefe5724b47
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Log Message:
-----------
[LLVM][AArch64] Add register classes for Armv9.6 assembly (#111717)
Add new register classes/operands and their encoder/decoder behaviour
required for the new Armv9.6 instructions (see
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension).
This work is the basis ofthe 2024 Armv9.6 architecture update effort for
SME.
Co-authored-by: Caroline Concatto caroline.concatto at arm.com
Co-authored-by: Marian Lukac marian.lukac at arm.com
Co-authored-by: Momchil Velikov momchil.velikov at arm.com
Commit: e7302319b52e3d231216d54d10622b0698928a96
https://github.com/llvm/llvm-project/commit/e7302319b52e3d231216d54d10622b0698928a96
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/test/lib/Pass/CMakeLists.txt
Log Message:
-----------
[mlir] Fix shared build. NFC
Commit: 17e9752267ed9c81c8da87f3a6d0e01f130b0d04
https://github.com/llvm/llvm-project/commit/17e9752267ed9c81c8da87f3a6d0e01f130b0d04
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/test/lib/Pass/CMakeLists.txt
R mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/mlir-spirv-cpu-runner/double.mlir
M mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
Log Message:
-----------
Revert "[mlir][mlir-spirv-cpu-runner] Move MLIR pass pipeline to mlir-opt" (#113176)
Reverts llvm/llvm-project#111575
This caused build failures:
https://lab.llvm.org/buildbot/#/builders/138/builds/5244
Commit: c5ca1b8626db71fa7ac5d851fa3a0710641136ff
https://github.com/llvm/llvm-project/commit/c5ca1b8626db71fa7ac5d851fa3a0710641136ff
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/test/CodeGen/PowerPC/sat-add.ll
A llvm/test/CodeGen/PowerPC/uaddo-32.ll
A llvm/test/CodeGen/PowerPC/uaddo-64.ll
Log Message:
-----------
[PPC] Add custom lowering for uaddo (#110137)
Improve the codegen for uaddo node for i64 in 64-bit mode and i32 in
32-bit mode by custom lowering.
Commit: 900b6369e2f5fbc229371a142fdcd28b5280dbc0
https://github.com/llvm/llvm-project/commit/900b6369e2f5fbc229371a142fdcd28b5280dbc0
Author: Jake Egan <jake.egan at ibm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/log1p.ll
Log Message:
-----------
[AIX][test] XFAIL constant folding log1p test
Test added by commit 47a6da2d4dc7d996eb2678243ac566822d59e483 fails on the AIX bot. So XFAIL for now to investigate further.
Commit: 120e42d3135f558b5e0a73da1c6484571eeff941
https://github.com/llvm/llvm-project/commit/120e42d3135f558b5e0a73da1c6484571eeff941
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Improve metadata cleanup in LTO backend (#113039)
Previously we were attempting to remove the memprof-related metadata
when iterating through instructions in the LTO backend. However, we
missed some as there are a number of cases where we skip instructions,
or even entire functions. Simplify the cleanup and ensure all is removed
by doing a full sweep over all instructions after completing cloning.
This is largely NFC except with -memprof-report-hinted-sizes enabled,
because we were propagating and simplifying the metadata after inlining
in the LTO backend, which caused some stray messages as metadata was
re-converted to attributes.
Commit: 8417f6af54c8f6dcf5893ab1352b50bf33c5a1ba
https://github.com/llvm/llvm-project/commit/8417f6af54c8f6dcf5893ab1352b50bf33c5a1ba
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[win/asan] Fix instruction size for 44 0f b6 1a
movzx r11d,BYTE PTR [rdx]
is four bytes long.
Follow-up to #111638
Commit: 42ba452aa94e4da277842d8990ad958a6256e558
https://github.com/llvm/llvm-project/commit/42ba452aa94e4da277842d8990ad958a6256e558
Author: Spencer Abson <Spencer.Abson at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Log Message:
-----------
[NFC] Fix -WError for unused Encode/Decode ZK methods
Remove the unused functions and register classes from the change below
https://github.com/llvm/llvm-project/commit/4679583181a9032b4f7c6476c7a1bfefe5724b47
Commit: 9e03920cbf946e7ba282e99213707643a23ae5fb
https://github.com/llvm/llvm-project/commit/9e03920cbf946e7ba282e99213707643a23ae5fb
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/root-gather-reused-scalar.ll
Log Message:
-----------
[SLP]Ignore root gather node, when searching for reuses
Root gather/buildvector node should be ignored when SLP vectorizer tries
to find matching gather nodes, vectorized earlier. This node is
definitely the last one in the pipeline and it does not have users. It
may cause the compiler crash
Fixes #113143
Commit: 54c93aabec965469fe7db1f4391a190e3d640feb
https://github.com/llvm/llvm-project/commit/54c93aabec965469fe7db1f4391a190e3d640feb
Author: vporpo <vporpodas at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
Log Message:
-----------
[SandboxVec][Legality] Scaffolding for Legality (#112623)
This patch adds a LegalityResultWithReason class for describing the
reason why legality decided not to vectorize the code.
Commit: fc59f2cc0f191bb7a0706dfb65e3e46fef69f466
https://github.com/llvm/llvm-project/commit/fc59f2cc0f191bb7a0706dfb65e3e46fef69f466
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
A llvm/test/CodeGen/PowerPC/const-stov.ll
M llvm/test/CodeGen/PowerPC/load-and-splat.ll
M llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll
M llvm/test/CodeGen/PowerPC/ppc-32bit-build-vector.ll
Log Message:
-----------
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
Special case small int constant in the PPC custom lowering of
scalar_to_vector.
Commit: f1e455ed51be4f53462db87aa5d64dbd830e5de2
https://github.com/llvm/llvm-project/commit/f1e455ed51be4f53462db87aa5d64dbd830e5de2
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[NFC][Sema][OpenMP] Fix free-nonheap-object warning (#112942)
This is one of the many PRs to fix errors with LLVM_ENABLE_WERROR=on.
Built by GCC 11.
Fix warning
In destructor ‘llvm::APInt::~APInt()’,
inlined from ‘llvm::APInt::~APInt()’ at
llvm-project/llvm/include/llvm/ADT/APInt.h:190:3,
inlined from ‘llvm::APSInt::~APSInt()’ at
llvm-project/llvm/include/llvm/ADT/APSInt.h:23:21,
inlined from ‘bool
checkOMPArraySectionConstantForReduction(clang::ASTContext&, const
clang::ArraySectionExpr*, bool&, llvm::SmallVectorImpl<llvm::APSInt>&)’
at llvm-project/clang/lib/Sema/SemaOpenMP.cpp:18357:45,
inlined from ‘bool actOnOMPReductionKindClause(clang::Sema&,
{anonymous}::DSAStackTy*, clang::OpenMPClauseKind,
llvm::ArrayRef<clang::Expr*>, clang::SourceLocation,
clang::SourceLocation, clang::SourceLocation, clang::SourceLocation,
clang::CXXScopeSpec&, const clang::DeclarationNameInfo&,
llvm::ArrayRef<clang::Expr*>, {anonymous}::ReductionData&)’ at
llvm-project/clang/lib/Sema/SemaOpenMP.cpp:18715:68:
llvm-project/llvm/include/llvm/ADT/APInt.h:192:18: error: ‘void operator
delete [](void*)’ called on a pointer to an unallocated object ‘1’
[-Werror=free-nonheap-object]
192 | delete[] U.pVal;
| ^~~~
Commit: d4630ae5ed678e50f4758d0fb7a6875494f690e5
https://github.com/llvm/llvm-project/commit/d4630ae5ed678e50f4758d0fb7a6875494f690e5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
Log Message:
-----------
[Vectorize] Fix a warning
This patch fixes:
llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h:85:16:
error: private field 'Reason' is not used
[-Werror,-Wunused-private-field]
Commit: 006fb0904d8e549476342de4b749792f73b3af85
https://github.com/llvm/llvm-project/commit/006fb0904d8e549476342de4b749792f73b3af85
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[gn build] Port 54c93aabec96
Commit: 3277c7cd28154e33637a168acb26cea7ac1f7fff
https://github.com/llvm/llvm-project/commit/3277c7cd28154e33637a168acb26cea7ac1f7fff
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
Log Message:
-----------
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.
Commit: ac9ee618572537bcd77c58899aaab1d41dbad206
https://github.com/llvm/llvm-project/commit/ac9ee618572537bcd77c58899aaab1d41dbad206
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeDataValues.cpp
M mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
[acc] Improve LegalizeDataValues pass to handle data constructs (#112990)
Renames LegalizeData to LegalizeDataValues since this pass fixes up SSA
values. LegalizeData suggested that it fixed data mapping.
This change also adds support to fix up ssa values for data clause
operations. Effectively, compute regions within a data region use the
ssa values from data operations also. The ssa values within data regions
but not within compute regions are not updated.
This change is to support the requirement in the OpenACC spec which
notes that a visible data clause is not just one on the current compute
construct but on the lexically containing data construct or visible
declare directive.
Commit: dcbf2c2ca078367fcd84feae9a51226b9761117a
https://github.com/llvm/llvm-project/commit/dcbf2c2ca078367fcd84feae9a51226b9761117a
Author: Farzon Lotfi <1802579+farzonl at users.noreply.github.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Transforms/Scalar/Scalarizer.cpp
A llvm/test/CodeGen/DirectX/split-double.ll
A llvm/test/Transforms/Scalarizer/frexp.ll
Log Message:
-----------
[Scalarizer][DirectX] support structs return types (#111569)
Based on this RFC:
https://discourse.llvm.org/t/rfc-allow-the-scalarizer-pass-to-scalarize-vectors-returned-in-structs/82306
LLVM intrinsics do not support out params. To get around this limitation
implementers will make intrinsics return structs to capture a return
type and an out param. This implementation detail should not impact
scalarization since these cases should be elementwise operations.
## Three changes are needed.
- The CallInst visitor needs to be updated to handle Structs
- A new visitor is needed for `ExtractValue` instructions
- finsh needs to be update to handle structs so that insert elements are
properly propogated.
## Testing changes
- Add support for `llvm.frexp`
- Add support for `llvm.dx.splitdouble`
fixes https://github.com/llvm/llvm-project/issues/111437
Commit: 7eb8238a32516008476b717bc6a2be8c59f7f535
https://github.com/llvm/llvm-project/commit/7eb8238a32516008476b717bc6a2be8c59f7f535
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/TableGen/x86-fold-tables.td
Log Message:
-----------
[TableGen] Handle Windows line endings in x86-fold-tables.td test (#112997)
The x86-fold-tables.td has been failing for me and [in
CI](https://buildkite.com/llvm-project/github-pull-requests/builds/111277#0192a122-c5c9-4e4e-bc5b-7532fec99ae4)
if Git happens to decide to check out the baseline file with Windows
line endings.
This fix for this is to add the `--strip-trailing-cr` option to diff to
normalize the line endings before comparing them.
Commit: 8ae39c8e34de2d24c46827b324c76bac845c18b0
https://github.com/llvm/llvm-project/commit/8ae39c8e34de2d24c46827b324c76bac845c18b0
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
Log Message:
-----------
[MC] Fix llvm-mc unterminated string constants warning for Windows (#112995)
#98060 introduced a warning for unterminated string constants, however
it was only checking for `\n` which means that it produced strange
results on Windows (always blaming column 1) including having the
[associated test
fail](https://buildkite.com/llvm-project/github-pull-requests/builds/111277#0192a122-c5c9-4e4e-bc5b-7532fec99ae4)
if Git happened to use Windows newlines when creating the file.
This fix for this is to detect both `\r` and `\n`, but don't double-warn
for Windows newlines.
Commit: 766bd6f4d05a4b52892be4f1b740e67053a22ee6
https://github.com/llvm/llvm-project/commit/766bd6f4d05a4b52892be4f1b740e67053a22ee6
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
Log Message:
-----------
[AMDGPU] Avoid repeated map lookups (NFC) (#112819)
Commit: eaa7b385368fa7e3dad9b95411d04be55e71494e
https://github.com/llvm/llvm-project/commit/eaa7b385368fa7e3dad9b95411d04be55e71494e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Log Message:
-----------
[Transforms] Avoid repeated hash lookups (NFC) (#113120)
Commit: 30a402833f50b14148c8b963f3ffaaeaeea5fd78
https://github.com/llvm/llvm-project/commit/30a402833f50b14148c8b963f3ffaaeaeea5fd78
Author: Augusto Noronha <anoronha at apple.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/include/lldb/Symbol/TypeSystem.h
Log Message:
-----------
[lldb][NFC] Fix doxygen comment on top of GetMangledTypeName
Commit: ab07fc832009b678c0b24392ad7e02a8e5dd3932
https://github.com/llvm/llvm-project/commit/ab07fc832009b678c0b24392ad7e02a8e5dd3932
Author: Yijia Gu <yijiagu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] add missing dep in OpenAccTransforms
Commit: 2c331b35712e0fad93cf804674196b7c0e47ebd9
https://github.com/llvm/llvm-project/commit/2c331b35712e0fad93cf804674196b7c0e47ebd9
Author: Yijia Gu <yijiagu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] remove tab blank in OpenAccTransforms
Commit: 4de708e32e31ac32b924dfeb020086636700c0f7
https://github.com/llvm/llvm-project/commit/4de708e32e31ac32b924dfeb020086636700c0f7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj
R lldb/tools/debugserver/source/MacOSX/stack_logging.h
Log Message:
-----------
[lldb] Remove stack_logging.h (#112987)
This file is covered under the Apple open source license rather than the
LLVM license. Presumably this was an oversight, but it doesn't really
matter as this file is unused. Remove it altogether.
Commit: ed5072ee28809abf0f140ca15df549a418bb5c69
https://github.com/llvm/llvm-project/commit/ed5072ee28809abf0f140ca15df549a418bb5c69
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lld/test/MachO/icf-safe-thunks-dwarf.ll
M lld/test/MachO/icf-safe-thunks.ll
Log Message:
-----------
[NFC][lld-macho] Generate test bodies for icf-safe-thunk tests (#111927)
Autogenerate `.ll` code from cpp code in some `-icf-safe-thunk` tests
using `update_test_body.py`
```
PATH=build/bin:$PATH llvm/utils/update_test_body.py lld/test/MachO/icf-safe-thunks.ll lld/test/MachO/icf-safe-thunks-dwarf.ll
```
https://llvm.org/docs/TestingGuide.html#elaborated-tests
I recently became aware of this tool and I wanted to practice using it.
This also allows to remove the custom instructions to generate the `.ll`
code.
Commit: 59528bbc73644f7c9e08406cf61a21b5dd8fe3b8
https://github.com/llvm/llvm-project/commit/59528bbc73644f7c9e08406cf61a21b5dd8fe3b8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
Log Message:
-----------
[nfc][msan] Reorder flags in RUN: (#113196)
Commit: cafeacff2c6367a229aa8b65be99835177f5c3be
https://github.com/llvm/llvm-project/commit/cafeacff2c6367a229aa8b65be99835177f5c3be
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
Log Message:
-----------
[nfc][msan] Remove RUN: duplicates (#113197)
Commit: 7dc2542ac24fcae89dfd179fa58c4ec4fb959e2b
https://github.com/llvm/llvm-project/commit/7dc2542ac24fcae89dfd179fa58c4ec4fb959e2b
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/pr32842.ll
Log Message:
-----------
[nfc][msan] Fix old typo in test (#113198)
Commit: f58ce1152703ca753794b8cef36da30bd2668d0f
https://github.com/llvm/llvm-project/commit/f58ce1152703ca753794b8cef36da30bd2668d0f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/TableGen/Record.h
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/SetTheory.cpp
M llvm/lib/TableGen/TGParser.cpp
Log Message:
-----------
[NFC][TableGen] Use auto when initializing variables with cast<> (#113171)
Use `auto` when initializing a variable with `cast<>`. Remove some
unneeded `const_cast` (since all Init pointers are now const).
Commit: e6ada7162e25ab28f6e588fba23f0c11dd1238b5
https://github.com/llvm/llvm-project/commit/e6ada7162e25ab28f6e588fba23f0c11dd1238b5
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/CalcSpillWeights.h
M llvm/include/llvm/CodeGen/LiveIntervals.h
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
A llvm/test/CodeGen/AArch64/regalloc-spill-weight-basic.ll
Log Message:
-----------
[regalloc][basic] Change spill weight for optsize funcs (#112960)
Change the spill weight calculations for `optsize` functions to remove
the block frequency multiplier. For those functions, we do not want to
consider the runtime cost of spilling, only the codesize cost.
I built a large app with the basic and greedy (default) register
allocator enabled.
| Regalloc Type | Uncompressed Size Delta | Compressed Size Delta |
| - | - | - |
| Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) |
| Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) |
Since I only saw a size win with the basic register allocator, I decided
to only change the behavior for that type.
Commit: 40ea92c859234d536553cf26650e89d6e52071c6
https://github.com/llvm/llvm-project/commit/40ea92c859234d536553cf26650e89d6e52071c6
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/unittests/ScriptInterpreter/Lua/ScriptInterpreterTests.cpp
Log Message:
-----------
[lldb] Update ScriptInterpreterTests for CommandReturnObject API change
Commit: 44c98846220fce6b2fad72e7247ac5861d8262d5
https://github.com/llvm/llvm-project/commit/44c98846220fce6b2fad72e7247ac5861d8262d5
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M flang/lib/Parser/unparse.cpp
Log Message:
-----------
Replace `join` lambda with explicit calls to Walk
clang flags some issues with inline templates being undefined.
The problem may be legitimate, but in order to save time, the
template-lambda was removed altogether.
Commit: a51febdda82c5d4eebd6a73243221f9aa63bad12
https://github.com/llvm/llvm-project/commit/a51febdda82c5d4eebd6a73243221f9aa63bad12
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/CXX/drs/cwg9xx.cpp
M clang/www/cxx_dr_status.html
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/rtsan/CMakeLists.txt
R compiler-rt/lib/rtsan/rtsan_interceptors.cpp
A compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
R compiler-rt/lib/rtsan/tests/rtsan_test_interceptors.cpp
A compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Fir/OpenACC/legalize-data.fir
M lld/test/MachO/icf-safe-thunks-dwarf.ll
M lld/test/MachO/icf-safe-thunks.ll
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj
R lldb/tools/debugserver/source/MacOSX/stack_logging.h
M lldb/unittests/ScriptInterpreter/Lua/ScriptInterpreterTests.cpp
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/CalcSpillWeights.h
M llvm/include/llvm/CodeGen/LiveIntervals.h
M llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/TableGen/Record.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/RegAllocBasic.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/SetTheory.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/Scalarizer.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/qshrn.ll
A llvm/test/CodeGen/AArch64/regalloc-spill-weight-basic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
A llvm/test/CodeGen/DirectX/split-double.ll
M llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
A llvm/test/CodeGen/PowerPC/const-stov.ll
M llvm/test/CodeGen/PowerPC/load-and-splat.ll
M llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll
M llvm/test/CodeGen/PowerPC/ppc-32bit-build-vector.ll
M llvm/test/CodeGen/PowerPC/sat-add.ll
A llvm/test/CodeGen/PowerPC/uaddo-32.ll
A llvm/test/CodeGen/PowerPC/uaddo-64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
M llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
M llvm/test/Instrumentation/MemorySanitizer/pr32842.ll
A llvm/test/MC/AArch64/LSFE/directive-arch-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension.s
A llvm/test/MC/AArch64/LSFE/directive-cpu-negative.s
A llvm/test/MC/AArch64/LSFE/directive-cpu.s
A llvm/test/MC/AArch64/LSFE/ldfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfadd.s
A llvm/test/MC/AArch64/LSFE/ldfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmax.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm.s
A llvm/test/MC/AArch64/LSFE/ldfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmin.s
A llvm/test/MC/AArch64/LSFE/ldfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfminnm.s
A llvm/test/MC/AArch64/LSFE/stfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfadd.s
A llvm/test/MC/AArch64/LSFE/stfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmax.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm.s
A llvm/test/MC/AArch64/LSFE/stfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmin.s
A llvm/test/MC/AArch64/LSFE/stfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfminnm.s
M llvm/test/TableGen/x86-fold-tables.td
M llvm/test/ThinLTO/X86/memprof-icp.ll
M llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
M llvm/test/Transforms/InstCombine/log1p.ll
A llvm/test/Transforms/SLPVectorizer/X86/root-gather-reused-scalar.ll
A llvm/test/Transforms/Scalarizer/frexp.ll
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeDataValues.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/lib/Pass/CMakeLists.txt
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kparzysz/spr/i01-flang-iterator-modifier
Compare: https://github.com/llvm/llvm-project/compare/4cf2b44cd11b...a51febdda82c
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