[all-commits] [llvm/llvm-project] 2a6b09: [LV] Use type from InsertPos for cost computation ...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Mon Oct 21 10:54:28 PDT 2024
Branch: refs/heads/users/vitalybuka/spr/main.nfcmsan-fix-old-typo-in-test
Home: https://github.com/llvm/llvm-project
Commit: 2a6b09e0d3d3c1a05d3d5165202a6e68900974b1
https://github.com/llvm/llvm-project/commit/2a6b09e0d3d3c1a05d3d5165202a6e68900974b1
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-10-18 (Fri, 18 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
Log Message:
-----------
[LV] Use type from InsertPos for cost computation of interleave groups.
Previously the legacy cost model would pick the type for the cost
computation depending on the order of the members in the input IR.
This is incompatible with the VPlan-based cost model (independent of
original IR order) and also doesn't match code-gen, which uses the type
of the insert position.
Update the legacy cost model to use the type (and address space) from
the Group's insert position.
This brings the legacy cost model in line with the legacy cost model and
fixes a divergence between both models.
Note that the X86 cost model seems to assign different costs to groups
with i64 and double types. Added a TODO to check.
Fixes https://github.com/llvm/llvm-project/issues/112922.
Commit: 0a6def62c2807d213e2b80f23c4a14cb9302f3fd
https://github.com/llvm/llvm-project/commit/0a6def62c2807d213e2b80f23c4a14cb9302f3fd
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M mlir/tools/mlir-tblgen/OpDocGen.cpp
Log Message:
-----------
[mlir][doc] Emit `\n` if description not end with `\n`. (#112898)
This PR addresses a markdown formatting issue by ensuring a `\n` is
emitted if the description string does not already end with one. Fixes
#112672.
Commit: cf4442e6b10280a90982a161b91319ebd1235718
https://github.com/llvm/llvm-project/commit/cf4442e6b10280a90982a161b91319ebd1235718
Author: Job Henandez Lara <jobhdezlara93 at gmail.com>
Date: 2024-10-18 (Fri, 18 Oct 2024)
Changed paths:
M libc/hdr/stdio_overlay.h
M libc/hdr/wchar_overlay.h
Log Message:
-----------
[libc] temporaliy disable __USE_EXTERN_INLINES and set __USE_FORITFY_LEVEL to 1 before including in overlay mode (#113012)
Commit: 85df28180bd38d3fd5356efe6022eebec31e0814
https://github.com/llvm/llvm-project/commit/85df28180bd38d3fd5356efe6022eebec31e0814
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-10-18 (Fri, 18 Oct 2024)
Changed paths:
A clang/test/Format/dry-run-warning.cpp
M clang/tools/clang-format/ClangFormat.cpp
Log Message:
-----------
[clang-format] Fix a bug that always returns error for JSON (#112839)
Fixes #108556.
Commit: 5406834cdaa6d26b98484d634df579606ae02229
https://github.com/llvm/llvm-project/commit/5406834cdaa6d26b98484d634df579606ae02229
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-10-18 (Fri, 18 Oct 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp
M flang/test/Fir/CUDA/cuda-register-func.fir
M flang/test/Fir/cuf-invalid.fir
Log Message:
-----------
[flang][cuda] Add cuf.register_module operation (#112971)
Add a new operation to register the fatbin and pass it to
`cuf.register_kernel`
Commit: d37bc32a65651e647148236ffb9728ea2e77eac3
https://github.com/llvm/llvm-project/commit/d37bc32a65651e647148236ffb9728ea2e77eac3
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-10-18 (Fri, 18 Oct 2024)
Changed paths:
A flang/include/flang/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.h
M flang/include/flang/Optimizer/Support/InitFIR.h
A flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Optimizer/Dialect/CUF/CMakeLists.txt
A flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/runtime/CUDA/CMakeLists.txt
A flang/runtime/CUDA/registration.cpp
Log Message:
-----------
[flang][cuda] Translate cuf.register_kernel and cuf.register_module (#112972)
Add LLVM IR Translation for `cuf.register_module` and
`cuf.register_kernel`. These are lowered to function call to the CUF
runtime entries.
Commit: 3d84b74cb3543428c35fc39e889684497286d482
https://github.com/llvm/llvm-project/commit/3d84b74cb3543428c35fc39e889684497286d482
Author: Augusto Noronha <anoronha at apple.com>
Date: 2024-10-18 (Fri, 18 Oct 2024)
Changed paths:
M lldb/include/lldb/Symbol/CompilerType.h
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/Symbol/TypeSystem.cpp
Log Message:
-----------
[lldb] Add GetMangledTypeName to TypeSystem/CompilerType (#113006)
Swift types have mangled names, so there should be a way to read those
from the compiler type.
This patch upstreams these two changes from swiftlang/llvm-project
(which were added there since at least 2016).
Commit: d8b17f2fb6129dba99c2ef843e5c38cc4414ae67
https://github.com/llvm/llvm-project/commit/d8b17f2fb6129dba99c2ef843e5c38cc4414ae67
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
[GlobalISel] Combine G_UNMERGE_VALUES with anyext and build vector (#112370)
G_UNMERGE_VALUES (G_ANYEXT (G_BUILD_VECTOR))
ag G_UNMERGE_VALUES llvm/test/CodeGen/AArch64/GlobalISel | grep ANYEXT
[ANYEXT] is build vector or shuffle vector
Prior art:
https://reviews.llvm.org/D87117
https://reviews.llvm.org/D87166
https://reviews.llvm.org/D87174
https://reviews.llvm.org/D87427
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR
[[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF1]](s8),
[[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT
[[BUILD_VECTOR2]](<8 x s8>)
; CHECK-NEXT: [[UV10:%[0-9]+]]:_(<4 x s16>), [[UV11:%[0-9]+]]:_(<4 x
s16>) = G_UNMERGE_VALUES
[[ANYEXT1]](<8 x s16>)
Test:
llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
Commit: 5e81437f2ba03ee0ab93b26a9654da9b95dab3b0
https://github.com/llvm/llvm-project/commit/5e81437f2ba03ee0ab93b26a9654da9b95dab3b0
Author: BrnBlrg <BenjaminAaronBlumer at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M clang/docs/analyzer/user-docs/CommandLineUsage.rst
Log Message:
-----------
[analyzer][doc] Fix typo in "translation unit" in analyzer doc CommandLineUsage.rst (#112966)
Commit: faed85b8e4961e853bfb10cd8ed1544e179ade0a
https://github.com/llvm/llvm-project/commit/faed85b8e4961e853bfb10cd8ed1544e179ade0a
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
Log Message:
-----------
[lldb][test][NFC] Document DYLIB_NAME Makefile variable (#112735)
Got caught out by this because simply specifying `DYLIB_CXX_SOURCES`
(without specifying `DYLIB_NAME`) resulted in linker errors because the
dylib was never built (and linked). We should probably make that a
Makefile error (though I haven't audited when exactly not specifying
`DYLIB_NAME` is valid; looked like that can happen when we specify
`FRAMEWORK`).
Commit: aa320600e2b7136f5156dd0c31f98ec0f8d5bce1
https://github.com/llvm/llvm-project/commit/aa320600e2b7136f5156dd0c31f98ec0f8d5bce1
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp
Log Message:
-----------
[lldb][ClangASTImporter][NFC] Emit a log message when we break MapImported invariant (#112748)
This patch emits a warning into the expression log when we call
`MapImported` on a decl which has already been imported, but with a new
`to` destination decl. In asserts builds this would lead to triggering
this [ASTImporter::MapImported
assertion](https://github.com/llvm/llvm-project/blob/6d7712a70c163d2ae9e1dc928db31fcb45d9e404/clang/lib/AST/ASTImporter.cpp#L10493-L10494).
In no-asserts builds we will likely crash, in potentially non-obvious
ways. The hope is that the log message will help in diagnosing this type
of issue in the field.
The underlying issue is discussed in more detail in:
https://github.com/llvm/llvm-project/pull/112566.
In a non-asserts build, the last few expression log entries would look
as follows:
```
CompleteTagDecl on (ASTContext*)scratch ASTContext Completing (TagDecl*)0x00000001132d31d0 named Foo
CTD Before:
CXXRecordDecl 0x1132d31d0 <<invalid sloc>> <invalid sloc> <undeserialized declarations> struct Foo
[ClangASTImporter] WARNING: overwriting an already imported decl '0x000000014378fd80' ('Foo') from '0x0000000143790c00' with 0x00000001132d31d0. Likely due to a name conflict when importing 'Foo'.
[ClangASTImporter] Imported (FieldDecl*)0x0000000143790220, named service (from (Decl*)0x0000000143791270), metadata 271
[ClangASTImporter] Decl has no origin information in (ASTContext*)0x00000001132c8c00
FindExternalLexicalDecls on (ASTContext*)0x0000000143c1f600 'scratch ASTContext' in 'Foo' (CXXRecordDecl*)0x000000014378FD80
FELD Original decl (ASTContext*)0x00000001132c8c00 (Decl*)0x0000000143790c00:
CXXRecordDecl 0x143790c00 <<invalid sloc>> <invalid sloc> struct Foo definition
|-DefinitionData pass_in_registers aggregate standard_layout trivially_copyable pod trivial literal
| |-DefaultConstructor exists trivial needs_implicit
| |-CopyConstructor simple trivial has_const_param needs_implicit implicit_has_const_param
| |-MoveConstructor exists simple trivial needs_implicit
| |-CopyAssignment simple trivial has_const_param needs_implicit implicit_has_const_param
| |-MoveAssignment exists simple trivial needs_implicit
| `-Destructor simple irrelevant trivial needs_implicit
|-FieldDecl 0x143791270 <<invalid sloc>> <invalid sloc> service 'Service *'
`-FieldDecl 0x1437912c8 <<invalid sloc>> <invalid sloc> mach_endpoint 'int'
FELD Adding [to CXXRecordDecl Foo] lexical FieldDecl FieldDecl 0x143791270 <<invalid sloc>> <invalid sloc> service 'Service *'
FELD Adding [to CXXRecordDecl Foo] lexical FieldDecl FieldDecl 0x1437912c8 <<invalid sloc>> <invalid sloc> mach_endpoint 'int'
[ClangASTImporter] Imported (FieldDecl*)0x0000000143790278, named mach_endpoint (from (Decl*)0x00000001437912c8), metadata 280
[ClangASTImporter] Decl has no origin information in (ASTContext*)0x00000001132c8c00
```
Note how we start "completing" `Foo`. Then emit our new `WARNING`.
Shortly after, we crash, and the log abruptly ends.
rdar://135551810
Commit: 1bbf3a37056761ec407031431e28f856428566f0
https://github.com/llvm/llvm-project/commit/1bbf3a37056761ec407031431e28f856428566f0
Author: Hui <hui.xie1990 at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M libcxx/include/__iterator/reverse_iterator.h
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/greater-equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/greater.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/less-equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/less.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/not-equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/assign.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/ctor.default.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/ctor.iter.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/ctor.reverse_iterator.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.conv/base.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.elem/arrow.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.elem/bracket.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.elem/dereference.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/decrement-assign.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/increment-assign.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/minus.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/plus.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/postdecrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/postincrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/predecrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/preincrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/make_reverse_iterator.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/minus.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/plus.pass.cpp
Log Message:
-----------
[libc++] Fix `reverse_iterator` when underlying is c++20 `bidirectional_iterator` but not `Cpp17BidirectionalIterator` (#112100)
`reverse_iterator` supports either c++20 `bidirectional_iterator` or
`Cpp17BidirectionalIterator `
http://eel.is/c++draft/reverse.iter.requirements
The current `reverse_iterator` uses `std::prev` in its `operator->`,
which only supports the `Cpp17BidirectionalIterator` properly.
If the underlying iterator is c++20 `bidirectional_iterator` but does
not satisfy the named requirement `Cpp17BidirectionalIterator`,
(examples are `zip_view::iterator`, `flat_map::iterator`), the current
`std::prev` silently compiles but does a no-op and returns the same
iterator back. So `reverse_iterator::operator->` will silently give a
wrong answer.
Even if we fix the behaviour of `std::prev`, at best, we could fail to
compile the code. But this is not ok, because we need to support this
kind of iterators in `reverse_iterator`.
The solution is simply to not use `std::prev`.
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 1775b98de719299b653c12999d49ca04a9f4f65b
https://github.com/llvm/llvm-project/commit/1775b98de719299b653c12999d49ca04a9f4f65b
Author: Finlay <finlay.marno at codeplay.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
A mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
Log Message:
-----------
[mlir][spirv] Add spirv-to-llvm conversion for OpControlBarrier (#111864)
The conversion is based on the expected llvm function from the
LLVM/SPIRV translation tool.
Commit: 8fe49b0bbef5134c87adc2719165392fca1865c3
https://github.com/llvm/llvm-project/commit/8fe49b0bbef5134c87adc2719165392fca1865c3
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M mlir/docs/Dialects/Linalg/_index.md
Log Message:
-----------
[mlir][docs] Fix name of `mlir-linalg-ods-yaml-gen`(NFC) (#113029)
Commit: 5785cbb40570c3847aa994b2d2b7e03321eee7eb
https://github.com/llvm/llvm-project/commit/5785cbb40570c3847aa994b2d2b7e03321eee7eb
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/ARM/fmuladd-soft-float.ll
A llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
A llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
A llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll
A llvm/test/CodeGen/X86/fmuladd-soft-float.ll
Log Message:
-----------
[llvm] Ensure that soft float targets don't emit `fma()` libcalls. (#106615)
The previous behavior could be harmful in some edge cases, such as
emitting a call to `fma()` in the `fma()` implementation itself.
Do this by just being more accurate in `isFMAFasterThanFMulAndFAdd()`.
This was already done for PowerPC; this commit just extends that to Arm,
z/Arch, and x86. MIPS and SPARC already got it right, but I added tests
for them too, for good measure.
Note: I don't have commit access.
Commit: 5aec88f0e6920b27dbc6cf7b4625088291441210
https://github.com/llvm/llvm-project/commit/5aec88f0e6920b27dbc6cf7b4625088291441210
Author: Nico Weber <thakis at chromium.org>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M compiler-rt/lib/hwasan/CMakeLists.txt
M llvm/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gn
Log Message:
-----------
[hwasan], [gn]: Fix formatting of hwasan cmake; re-sync gn file for b515d9ea1e43
Commit: 0f0a96b8621fcc8e1d6b6a3d047c263bb17a7f39
https://github.com/llvm/llvm-project/commit/0f0a96b8621fcc8e1d6b6a3d047c263bb17a7f39
Author: Youngsuk Kim <youngsuk.kim at hpe.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M clang/test/CodeGenCUDA/bf16.cu
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/addr-mode.ll
M llvm/test/CodeGen/NVPTX/aggregate-return.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
M llvm/test/CodeGen/NVPTX/chain-different-as.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-mad.ll
M llvm/test/CodeGen/NVPTX/compute-ptx-value-vts.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/dot-product.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i128-param.ll
M llvm/test/CodeGen/NVPTX/i128-retval.ll
M llvm/test/CodeGen/NVPTX/i128-struct.ll
M llvm/test/CodeGen/NVPTX/i128.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/jump-table.ll
M llvm/test/CodeGen/NVPTX/ldparam-v4.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-alloca.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/mulhi-intrins.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/param-load-store.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/param-vectorize-device.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
M llvm/test/CodeGen/NVPTX/sad-intrins.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/store-undef.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/tid-range.ll
M llvm/test/CodeGen/NVPTX/unaligned-param-load-store.ll
M llvm/test/CodeGen/NVPTX/unfold-masked-merge-vector-variablemask.ll
M llvm/test/CodeGen/NVPTX/vaargs.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vec-param-load.ll
M llvm/test/CodeGen/NVPTX/vector-args.ll
M llvm/test/CodeGen/NVPTX/vector-call.ll
M llvm/test/CodeGen/NVPTX/vector-returns.ll
M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
M llvm/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
Log Message:
-----------
[llvm][NVPTX] Strip unneeded '+0' in PTX load/store (#113017)
Remove the extraneous '+0' immediate offset part in PTX load/stores, to
improve readability of output PTX code.
Commit: 02bf3b54c02643069ad1a952c19f97cab00a3241
https://github.com/llvm/llvm-project/commit/02bf3b54c02643069ad1a952c19f97cab00a3241
Author: Felix Schneider <fx.schn at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Dialect/Linalg/roundtrip.mlir
Log Message:
-----------
[mlir][linalg] Add quantized conv2d operator with FCHW,NCHW order (#107740)
This patch adds a quantized version of the `linalg.conv2d_nchw_fchw` Op.
This is the "channel-first" ordering typically used by PyTorch and
others.
Commit: 697a455e6fecf364c1ac4ff9874aefddf2952454
https://github.com/llvm/llvm-project/commit/697a455e6fecf364c1ac4ff9874aefddf2952454
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lldb/include/lldb/Core/Module.h
M lldb/source/Core/Module.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
A lldb/test/Shell/SymbolFile/DWARF/TestDedupWarnings.test
Log Message:
-----------
More aggressively deduplicate global warnings based on contents. (#112801)
I've been getting complaints from users being spammed by -gmodules
missing file warnings going out of control because each object file
depends on an entire DAG of PCM files that usually are all missing at
once. To reduce this problem, this patch does two things:
1. Module now maintains a DenseMap<hash, once> that is used to display
each warning only once, based on its actual text.
2. The PCM warning itself is reworded to include less details, such as
the DIE offset, which is only useful to LLDB developers, who can get
this from the dwarf log if they need it. Because the detail is omitted
the hashing from (1) deduplicates the warnings.
rdar://138144624
Commit: f87f3ad6ea8bb80cba9ce009079e1b6c7486feac
https://github.com/llvm/llvm-project/commit/f87f3ad6ea8bb80cba9ce009079e1b6c7486feac
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/stage1.Dockerfile
Log Message:
-----------
[Github] Bump CI compiler version to 19.1.2 (#113016)
Commit: ef91cd3f018411e0ba7989003d7617041e35f650
https://github.com/llvm/llvm-project/commit/ef91cd3f018411e0ba7989003d7617041e35f650
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.gfx10.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
Log Message:
-----------
AMDGPU: Handle folding frame indexes into add with immediate (#110738)
Commit: 06fce61e03d87fcd6b3c2dfb187cdeeaa0d1e20e
https://github.com/llvm/llvm-project/commit/06fce61e03d87fcd6b3c2dfb187cdeeaa0d1e20e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/lib/Target/X86/X86.td
Log Message:
-----------
[X86] X86.td - whitespace cleanup. NFC.
Commit: 93ec08d62971d51a239fba8468d3cf9cb9e54fb0
https://github.com/llvm/llvm-project/commit/93ec08d62971d51a239fba8468d3cf9cb9e54fb0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[DAG] Move SIGN_EXTEND_INREG constant folding inside FoldConstantArithmetic
Update visitSIGN_EXTEND_INREG to call FoldConstantArithmetic instead of getNode.
Commit: 093d4db2f3c874d4683fb01194b00dbb20e5c713
https://github.com/llvm/llvm-project/commit/093d4db2f3c874d4683fb01194b00dbb20e5c713
Author: Campbell Barton <ideasman42 at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M clang/tools/clang-format/clang-format.el
Log Message:
-----------
Add "clang-format-on-save-mode" minor mode to clang-format.el (#104533)
Add an minor mode which can be optionally used to run clang-format on
save.
Formatting before saving works well and is convenient to avoid having to
remember to manually run clang format.
I've written this as it's own package but it's probably better if the
functionality is supported by clang-format.el.
See: https://github.com/melpa/melpa/pull/8762
Commit: 10f6d01e3d6cd6963bb2ec8729ab4f0aff9fdb5f
https://github.com/llvm/llvm-project/commit/10f6d01e3d6cd6963bb2ec8729ab4f0aff9fdb5f
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
Log Message:
-----------
[GlobalISel][AArch64] Legalize G_EXTRACT_SUBVECTOR (#112946)
for future combines
Commit: 8819267747c868309d606f58cb616b05217622eb
https://github.com/llvm/llvm-project/commit/8819267747c868309d606f58cb616b05217622eb
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Log Message:
-----------
[InstCombine] Simplify code with SmallMapVector::operator[] (NFC) (#113022)
Commit: ca9f396cac0371a398eeef73182987a55a21e4a1
https://github.com/llvm/llvm-project/commit/ca9f396cac0371a398eeef73182987a55a21e4a1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lldb/source/Core/DataFileCache.cpp
Log Message:
-----------
[lldb] Avoid repeated hash lookups (NFC) (#113024)
Commit: f4136b326514b0732054e17eadc646b45925192d
https://github.com/llvm/llvm-project/commit/f4136b326514b0732054e17eadc646b45925192d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
Log Message:
-----------
[llvm-diff] Avoid repeated hash lookups (NFC) (#113025)
Commit: b26df3e463cd1d65adadcd469fcd4b203484e39f
https://github.com/llvm/llvm-project/commit/b26df3e463cd1d65adadcd469fcd4b203484e39f
Author: Martin Storsjö <martin at martin.st>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
Log Message:
-----------
Revert "[DAG] isConstantIntBuildVectorOrConstantInt - peek through bitcasts (#112710)"
This reverts commit a630771b28f4b252e2754776b8f3ab416133951a.
This caused compilation to hang for Windows/ARM, see
https://github.com/llvm/llvm-project/pull/112710 for details.
Commit: 2eb1699184cf4d5de69f7825f66d7b3c04827f77
https://github.com/llvm/llvm-project/commit/2eb1699184cf4d5de69f7825f66d7b3c04827f77
Author: Tor Shepherd <tor.aksel.shepherd at gmail.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M clang-tools-extra/clangd/Config.h
M clang-tools-extra/clangd/ConfigCompile.cpp
M clang-tools-extra/clangd/ConfigFragment.h
M clang-tools-extra/clangd/ConfigYAML.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
Log Message:
-----------
[clangd] Add inlay hints for default function arguments (#95712)
The new inlay hints have the `DefaultArguments` kind and can be enabled in config similar to other inlay kint kinds.
Commit: dde26e361f50df4b999ac117222c74f2c100f817
https://github.com/llvm/llvm-project/commit/dde26e361f50df4b999ac117222c74f2c100f817
Author: Xing Xue <xingxue at outlook.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M libunwind/src/UnwindCursor.hpp
Log Message:
-----------
[libunwind][AIX] Call dlclose only when dlsym() fails (#112768)
The personality routine `__xlcxx_personality_v0` in `libc++abi` is
hard-coded in the unwinder as the handler for EH in applications
generated by the legacy IBM C++ compiler. The symbol is resolved
dynamically using `dlopen` to avoid a hard dependency of `libunwind` on
`libc++abi` for cases such as non-C++ applications. However, `dlclose`
was incorrectly called after `dlsym` succeeded, potentially invalidating
the function pointer obtained from `dlsym` when the memory allocated for
the `dlopen` is reclaimed. This PR changes to call `dlclose` only when
`dlsym` fails.
Commit: cd938bf3279b6d2f1c0a8c82b6371a384d744378
https://github.com/llvm/llvm-project/commit/cd938bf3279b6d2f1c0a8c82b6371a384d744378
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lldb/include/lldb/Target/Language.h
M lldb/source/Target/ThreadPlanStepOverRange.cpp
Log Message:
-----------
[lldb] Introduce Language::AreEquivalentFunctions (#112720)
This allows languages to provide an opinion on whether two symbol
contexts are equivalent (i.e. belong to the same function).
It is useful to drive the comparisons done by stepping plans that need
to ensure symbol contexts obtained from different points in time are
actually the same.
Commit: 2deb3a26fa47a4640962489e5473726d7a8bf12b
https://github.com/llvm/llvm-project/commit/2deb3a26fa47a4640962489e5473726d7a8bf12b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Fixup IV users only once during epilogue vectorization. (NFC)
Induction users only need to be updated when vectorizing the epilogue.
Avoid running fixupIVUsers when vectorizing the main loop during
epilogue vectorization.
Commit: fe8af49a1bf73055941d7aba5d1d2f8e894e8022
https://github.com/llvm/llvm-project/commit/fe8af49a1bf73055941d7aba5d1d2f8e894e8022
Author: Fangrui Song <i at maskray.me>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Pass Ctx & to Defined & CommonSymbol
Commit: cba5c77a715cfa5892c69b6c646556825932575b
https://github.com/llvm/llvm-project/commit/cba5c77a715cfa5892c69b6c646556825932575b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Mark unreachable code path when retrieving the scalar PH. (NFCI)
Commit: 1336e3d0b9a361fbbe2d97f225ef6757d20df51a
https://github.com/llvm/llvm-project/commit/1336e3d0b9a361fbbe2d97f225ef6757d20df51a
Author: c8ef <c8ef at outlook.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
A llvm/test/Transforms/InstCombine/ilogb.ll
Log Message:
-----------
[ConstantFold] Fold `ilogb` and `ilogbf` when the input parameter is a constant value. (#113014)
This patch adds support for constant folding for the `ilogb` and
`ilogbf` libc functions.
Commit: 4a011ac84fa16f7eed34c309bdac5591d9553da7
https://github.com/llvm/llvm-project/commit/4a011ac84fa16f7eed34c309bdac5591d9553da7
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/test/CoverageMapping/branch-constfolded.cpp
M clang/test/CoverageMapping/if.cpp
M clang/test/CoverageMapping/macro-expansion.c
M clang/test/CoverageMapping/mcdc-scratch-space.c
M clang/test/CoverageMapping/mcdc-system-headers.cpp
M clang/test/CoverageMapping/switch.cpp
M clang/test/CoverageMapping/switchmacro.c
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/test/tools/llvm-cov/branch-c-general.test
M llvm/tools/llvm-cov/CoverageExporterJson.cpp
M llvm/tools/llvm-cov/CoverageExporterLcov.cpp
M llvm/tools/llvm-cov/CoverageSummaryInfo.cpp
M llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
M llvm/tools/llvm-cov/SourceCoverageViewText.cpp
Log Message:
-----------
[Coverage] Introduce "partial fold" on BranchRegion (#112694)
Currently both True/False counts were folded. It lost the information,
"It is True or False before folding." It prevented recalling branch
counts in merging template instantiations.
In `llvm-cov`, a folded branch is shown as:
- `[True: n, Folded]`
- `[Folded, False n]`
In the case If `n` is zero, a branch is reported as "uncovered". This is
distinguished from "folded" branch. When folded branches are merged,
`Folded` may be dissolved.
In the coverage map, either `Counter` is `Zero`. Currently both were
`Zero`.
Since "partial fold" has been introduced, either case in `switch` is
omitted as `Folded`.
Each `case:` in `switch` is reported as `[True: n, Folded]`, since
`False` count doesn't show meaningful value.
When `switch` doesn't have `default:`, `switch (Cond)` is reported as
`[Folded, False: n]`, since `True` count was just the sum of `case`(s).
`switch` with `default` can be considered as "the statement that doesn't
have any `False`(s)".
Commit: 861bd36bce3c3e1384b87b0366cf83e2c022c325
https://github.com/llvm/llvm-project/commit/861bd36bce3c3e1384b87b0366cf83e2c022c325
Author: Fangrui Song <i at maskray.me>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lld/ELF/AArch64ErrataFix.cpp
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/AVR.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/SystemZ.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/MapFile.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Thunks.cpp
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Pass Ctx & to Symbol::getVA
Commit: 5d928ffce22d976b6594496f14351e00c2e4dd78
https://github.com/llvm/llvm-project/commit/5d928ffce22d976b6594496f14351e00c2e4dd78
Author: Fangrui Song <i at maskray.me>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lld/ELF/OutputSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Remove error-prone RelocationBaseSection::classof
Commit: e6625a2c106f6af468a98323b08c7ce3cf273485
https://github.com/llvm/llvm-project/commit/e6625a2c106f6af468a98323b08c7ce3cf273485
Author: Fangrui Song <i at maskray.me>
Date: 2024-10-19 (Sat, 19 Oct 2024)
Changed paths:
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/MapFile.cpp
M lld/ELF/Symbols.cpp
Log Message:
-----------
[ELF] Pass Ctx &
Commit: 11dad2fa5138a50d60a5a34a2c7e074b976820e2
https://github.com/llvm/llvm-project/commit/11dad2fa5138a50d60a5a34a2c7e074b976820e2
Author: Pranav Bhandarkar <pranav.bhandarkar at amd.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
A flang/test/Transforms/omp-maps-for-privatized-symbols.fir
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
Log Message:
-----------
[flang][OpenMP] - Add `MapInfoOp` instances for target private variables when needed (#109862)
This PR adds an OpenMP dialect related pass for FIR/HLFIR which creates
`MapInfoOp` instances for certain privatized symbols. For example, if an
allocatable variable is used in a private clause attached to a
`omp.target` op, then the allocatable variable's descriptor will be
needed on the device (e.g. GPU). This descriptor needs to be separately
mapped onto the device. This pass creates the necessary `omp.map.info`
ops for this.
Commit: e6c01432b6fb6077e1bdf2e0abf05d2c2dd3fd3e
https://github.com/llvm/llvm-project/commit/e6c01432b6fb6077e1bdf2e0abf05d2c2dd3fd3e
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M libc/newhdrgen/yaml/math.yaml
Log Message:
-----------
[libc][math][c23] Update newhdrgen for new _Float16 math functions (#113005)
Commit: ba1255def64a9c3c68d97ace051eec76f546eeb0
https://github.com/llvm/llvm-project/commit/ba1255def64a9c3c68d97ace051eec76f546eeb0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] Use FoldConstantArithmetic to constant fold (and (ext (and V, c1)), c2) -> (and (ext V), (and c1, (ext c2)))
Noticed while triaging the regression from #112710 noticed by @mstorsjo - don't rely on isConstantIntBuildVectorOrConstantInt+getNode to guarantee constant folding (if it fails to constant fold it will infinite loop), use FoldConstantArithmetic instead.
Commit: 94cddcfc1ca21958add4355653872e8eea2557b7
https://github.com/llvm/llvm-project/commit/94cddcfc1ca21958add4355653872e8eea2557b7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
A llvm/test/CodeGen/ARM/pr112710.ll
Log Message:
-----------
[ARM] Add reduced regression test for infinite-loop due to #112710
Commit: f0b3b6d15b2c0ee2cff2dd31dc075adb5d9a4ff7
https://github.com/llvm/llvm-project/commit/f0b3b6d15b2c0ee2cff2dd31dc075adb5d9a4ff7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
Log Message:
-----------
[DAG] isConstantIntBuildVectorOrConstantInt - peek through bitcasts (#112710) (REAPPLIED)
Alter both isConstantIntBuildVectorOrConstantInt + isConstantFPBuildVectorOrConstantFP to return a bool instead of the underlying SDNode, and adjust usage to account for this.
Update isConstantIntBuildVectorOrConstantInt to peek though bitcasts when attempting to find a constant, in particular this improves canonicalization of constants to the RHS on commutable instructions.
X86 is the beneficiary here as it often bitcasts rematerializable 0/-1 vector constants as vXi32 and bitcasts to the requested type
Minor cleanup that helps with #107423
Reapplied after regression fix ba1255def64a9c3c68d97ace051eec76f546eeb0
Commit: aa7f377c965ca79cf3022ddafe6cbd419bd52db5
https://github.com/llvm/llvm-project/commit/aa7f377c965ca79cf3022ddafe6cbd419bd52db5
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/clocale
M libcxx/include/cstdint
R libcxx/include/locale.h
M libcxx/include/module.modulemap
R libcxx/include/stdint.h
M libcxx/test/libcxx/depr/depr.c.headers/extern_c.pass.cpp
M libcxx/utils/libcxx/header_information.py
Log Message:
-----------
[libc++] Remove libc++'s own stdint.h and locale.h (#107436)
These headers are not doing anything beyond the system or compiler
provided equivalent headers, so there's no real reason to keep them
around. Reducing the number of C headers we provide in libc++ simplifies
our header layering and reduces the potential for confusion when headers
are layered incorrectly.
Commit: 5a47d48034dd3473eafd621b6f81647dd449f8e3
https://github.com/llvm/llvm-project/commit/5a47d48034dd3473eafd621b6f81647dd449f8e3
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port aa7f377c965c
Commit: 490b7d12f6bef2c399fca83e6a6dde31be021913
https://github.com/llvm/llvm-project/commit/490b7d12f6bef2c399fca83e6a6dde31be021913
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M clang/include/clang/AST/ExprCXX.h
M clang/lib/AST/ExprCXX.cpp
Log Message:
-----------
[clang][NFC] Pass const ASTContext& to CXXTypeidExpr API (#113083)
Commit: 2ce10f0491142863d3f21cd0adb312ab2cfed107
https://github.com/llvm/llvm-project/commit/2ce10f0491142863d3f21cd0adb312ab2cfed107
Author: Job Henandez Lara <jobhdezlara93 at gmail.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M libc/src/string/CMakeLists.txt
M libc/src/string/strcat.h
M libc/src/string/strcpy.h
M libc/src/string/strdup.h
M libc/src/string/strlcat.h
M libc/src/string/strlcpy.h
M libc/src/string/strlen.h
M libc/src/string/strncat.h
M libc/src/string/strndup.h
Log Message:
-----------
[libc] Remove the <string.h> header in libc/src and libc/test (#113076)
Commit: f13d3f72118b83e326169592e8f3c5962fd0eb29
https://github.com/llvm/llvm-project/commit/f13d3f72118b83e326169592e8f3c5962fd0eb29
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M clang/lib/Tooling/Inclusions/HeaderIncludes.cpp
Log Message:
-----------
[Tooling] Simplify code with StringMap::operator[] (NFC) (#113071)
Commit: 6ec113d4c35db934ec8fdb3d226d2d8e525a1f84
https://github.com/llvm/llvm-project/commit/6ec113d4c35db934ec8fdb3d226d2d8e525a1f84
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[Local] Avoid repeated map lookups (NFC) (#113072)
Commit: 8673d0e0673dd1a5e6f7a5df7509c45e33582987
https://github.com/llvm/llvm-project/commit/8673d0e0673dd1a5e6f7a5df7509c45e33582987
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M lldb/source/Interpreter/Options.cpp
Log Message:
-----------
[lldb] Avoid repeated map lookups (NFC) (#113073)
Commit: 5405ba50de6753e3969f4e6c690f53f2abb29b2f
https://github.com/llvm/llvm-project/commit/5405ba50de6753e3969f4e6c690f53f2abb29b2f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Check ia32_{pext,pdep} builtins for integer args (#113091)
Commit: b9cb9b3f0d1e891b385eb53f8414b29554fd9234
https://github.com/llvm/llvm-project/commit/b9cb9b3f0d1e891b385eb53f8414b29554fd9234
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/GVNSink.cpp
Log Message:
-----------
[GVNSink] Avoid repeated hash lookups (NFC) (#113023)
Commit: 3bddf85e5274b302915f77cec3e1ac60c9309ebd
https://github.com/llvm/llvm-project/commit/3bddf85e5274b302915f77cec3e1ac60c9309ebd
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/tools/sancov/sancov.cpp
Log Message:
-----------
[sancov] Avoid repeated map lookups (NFC) (#113026)
Commit: 2077fb80ffb58cd1060ec6a5475399c6ad297df3
https://github.com/llvm/llvm-project/commit/2077fb80ffb58cd1060ec6a5475399c6ad297df3
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
Log Message:
-----------
[mlir] Avoid repeated map lookups (NFC) (#113074)
Commit: d1401822e2d2753bed3ac597a42cc0b261de40a4
https://github.com/llvm/llvm-project/commit/d1401822e2d2753bed3ac597a42cc0b261de40a4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/lib/Support/VirtualFileSystem.cpp
Log Message:
-----------
[Support] Use a hetrogenous lookup with std::map (NFC) (#113075)
Commit: c2717a89b8437d041d532c7b2c535ca4f4b35872
https://github.com/llvm/llvm-project/commit/c2717a89b8437d041d532c7b2c535ca4f4b35872
Author: Martin Storsjö <martin at martin.st>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M compiler-rt/test/asan/TestCases/Windows/delay_dbghelp.cpp
Log Message:
-----------
[compiler-rt] [test] Remove an unintended grep parameter
This parameter seems unintentional here; we're trying to grep
the input on stdin, from the earlier stage in the pipeline.
Since a recent update on Github Actions runners, the previous
form (grepping a file, while piping in data on stdin) would fail
running the test, with the test runner Python script throwing
an exception when evaluating it:
File "D:\a\llvm-mingw\llvm-mingw\llvm-project\llvm\utils\lit\lit\TestRunner.py", line 935, in _executeShCmd
out = procs[i].stdout.read()
^^^^^^^^^^^^^^^^^^^^^^
File "C:\hostedtoolcache\windows\Python\3.12.7\x64\Lib\encodings\cp1252.py", line 23, in decode
return codecs.charmap_decode(input,self.errors,decoding_table)[0]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: a bytes-like object is required, not 'NoneType'
Commit: 20bda93e438c63fb68a8130b7f88090c558e99b7
https://github.com/llvm/llvm-project/commit/20bda93e438c63fb68a8130b7f88090c558e99b7
Author: Fawdlstty <fawdlstty at users.noreply.github.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
M llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
Log Message:
-----------
[TLI] Add basic support for scalbnxx (#112936)
This patch adds basic support for `scalbln, scalblnf, scalblnl, scalbn,
scalbnf, scalbnl`. Constant folding support will be submitted in a
subsequent patch.
Related issue: <#112631>
Commit: 173907b5d77115623f160978a95159e36e05ee6c
https://github.com/llvm/llvm-project/commit/173907b5d77115623f160978a95159e36e05ee6c
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-10-20 (Sun, 20 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Move logic to check if op is invariant to legacy cost model. (NFC)
This allows the function to be re-used in other places
Commit: d80b9cf713fd1698641c5b265de6b66618991476
https://github.com/llvm/llvm-project/commit/d80b9cf713fd1698641c5b265de6b66618991476
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/include/clang/ASTMatchers/ASTMatchersMacros.h
Log Message:
-----------
[Clang][ASTMatchers] Add visibility macros to variables declared by macros (#110206)
This will fix missing symbols for ASTMatchersTests on windows when
building with CLANG_LINK_CLANG and explicit visibility macros are used.
This PR depends on macros that will be be added in #108276
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and LLVM\Clang
plugins on window.
Commit: df8b785838a2db01b4d056e603f7317209accefb
https://github.com/llvm/llvm-project/commit/df8b785838a2db01b4d056e603f7317209accefb
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/test/AST/ByteCode/cxx98.cpp
Log Message:
-----------
[clang][bytecode] Narrow pointer in UO_Deref unary operators (#113089)
Otherwise we treat this like an array element even though we should
treat it as a single object.
Commit: 615a5eb02c91ef78f59461f842873617dd187450
https://github.com/llvm/llvm-project/commit/615a5eb02c91ef78f59461f842873617dd187450
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Check ai32_bextr builtins for integer args (#113128)
Commit: 9b49392d6edcdfcc59304350ebd4196be5180d4a
https://github.com/llvm/llvm-project/commit/9b49392d6edcdfcc59304350ebd4196be5180d4a
Author: Thirumalai Shaktivel <74826228+Thirumalai-Shaktivel at users.noreply.github.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/OpenMP/atomic06-empty.f90
A flang/test/Semantics/OpenMP/declare-simd-empty.f90
A flang/test/Semantics/OpenMP/threadprivate08-empty.f90
Log Message:
-----------
[Flang] Handle the source (scopes) for some OpenMP constructs (#109097)
Fixes: https://github.com/llvm/llvm-project/issues/82943
Fixes: https://github.com/llvm/llvm-project/issues/82942
Fixes: https://github.com/llvm/llvm-project/issues/85593
Commit: 3c5cea650dcef5e5aae8f4090f5b7f410b31fca2
https://github.com/llvm/llvm-project/commit/3c5cea650dcef5e5aae8f4090f5b7f410b31fca2
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
Log Message:
-----------
[AMDGPU]: Add implicit-def to the BB prolog (#112872)
IMPLICIT_DEF inserted for a wwm-register at the
very first block or the predecessor block where
it is used for sgpr spilling can appear at a block
begin that requires spill-insertion during per-lane
VGPR regalloc phase. The presence of the IMPLICIT_DEF
currently breaks the BB prolog.
Fixes: SWDEV-490717
Commit: 923b8eea644a4d1fed0f3e20677514cf3f4e0fcc
https://github.com/llvm/llvm-project/commit/923b8eea644a4d1fed0f3e20677514cf3f4e0fcc
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/complex.cpp
Log Message:
-----------
[clang][bytecode] Allow ArrayElemPtr ops on null pointers (#113132)
This regresses one of the _Complex test cases a bit, but since the
diagnostic output wasn't very good here in the first place, let's ignore
it.
Commit: d582442becf1507a243614ee7348ccbb51eade28
https://github.com/llvm/llvm-project/commit/d582442becf1507a243614ee7348ccbb51eade28
Author: Ronan Keryell <ronan.keryell at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-cxxfilt.rst
A llvm/test/tools/llvm-cxxfilt/quote.test
M llvm/tools/llvm-cxxfilt/Opts.td
M llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp
Log Message:
-----------
[llvm-cxxfilt] Add --quote option to quote demangled function names (#111871)
This is useful when looking at LLVM/MLIR assembly produced from C++
sources. For example
cir.call @_ZN3aie4tileILi1ELi4EE7programIZ4mainE3$_0EEvOT_(%2, %7) :
will be translated to
cir.call @"void aie::tile<1, 4>::program<main::$_0>(main::$_0&&)"(%2,
%7) : which can be parsed as valid MLIR by the right mlir-lsp-server.
If a symbol is already quoted, do not quote it more.
---------
Co-authored-by: James Henderson <jh7370 at my.bristol.ac.uk>
Commit: ba5676cf91f91bbddfacae06c036cf79af0f2088
https://github.com/llvm/llvm-project/commit/ba5676cf91f91bbddfacae06c036cf79af0f2088
Author: tangaac <tangyan01 at loongson.cn>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
Log Message:
-----------
[LoongArch] Minor refinement to monotonic atomic semantics. (#112681)
Don't use "_db" version AM instructions for LoongArch atomic memory
operations with monotonic semantics.
Commit: c77e836123d056d98051ee980003593706f9284d
https://github.com/llvm/llvm-project/commit/c77e836123d056d98051ee980003593706f9284d
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/test/CodeGen/attr-target-clones-riscv.c
M clang/test/CodeGen/attr-target-version-riscv.c
M clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
M clang/test/CodeGenCXX/attr-target-version-riscv.cpp
M clang/test/SemaCXX/attr-target-clones-riscv.cpp
M clang/test/SemaCXX/attr-target-version-riscv.cpp
Log Message:
-----------
[RISCV][FMV] Remove support for negative priority (#112161)
Ensure that target_version and target_clones do not accept negative
numbers for the priority feature.
Base on discussion on
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/85.
Commit: 6360652e9f5b5975d71c619abd981f102eeccec8
https://github.com/llvm/llvm-project/commit/6360652e9f5b5975d71c619abd981f102eeccec8
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
Log Message:
-----------
Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)
A reland but not an exact copy as `VRegInfo.Flags` from the parser is
now an int8 instead of a vector; so only need to copy over the value.
Commit: 911a6f2fcc719c46b5b392823473ba0bb5b1f4e1
https://github.com/llvm/llvm-project/commit/911a6f2fcc719c46b5b392823473ba0bb5b1f4e1
Author: Liu An <liuan at loongson.cn>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
M lldb/source/Plugins/Process/elf-core/CMakeLists.txt
A lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.cpp
A lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
M lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
A lldb/test/API/functionalities/postmortem/elf-core/linux-loongarch64.core
A lldb/test/API/functionalities/postmortem/elf-core/linux-loongarch64.out
Log Message:
-----------
[lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (#112296)
When using the lldb command 'target create --core' on the LoongArch64
architecture, this part of the code is required.
Commit: a705838394c367280f709d628f807bfdf33f9a4a
https://github.com/llvm/llvm-project/commit/a705838394c367280f709d628f807bfdf33f9a4a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn
Log Message:
-----------
[gn build] Port 911a6f2fcc71
Commit: 4f06f79c03f8392f63f4430fcfcaefa763cf5c93
https://github.com/llvm/llvm-project/commit/4f06f79c03f8392f63f4430fcfcaefa763cf5c93
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/utils/lit/lit/reports.py
Log Message:
-----------
[llvm][llvm-lit] Handle testsuite elapsed time being None
The time for all testsuites will always exist because lit
measures it itself. For a given testsuite, I guess that it
can be None if for example the suite is empty.
Commit: 8507dbaec3f644b8a0c6291f097800d82a4f4b16
https://github.com/llvm/llvm-project/commit/8507dbaec3f644b8a0c6291f097800d82a4f4b16
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/reports.py
A llvm/utils/lit/tests/unique-output-file.py
Log Message:
-----------
[llvm][llvm-lit] Add option to create unique result file names if results already exist (#112729)
When running a build like:
```
ninja check-clang check-llvm
```
Prior to my changes you ended up with one results file, in this specific case Junit XML:
```
results.xml
```
This would only include the last set of tests lit ran, which were for
llvm. To get around this, many CI systems will run one check target,
move the file away, then run another, somehow propgating the return code
as well.
```
rectode=0
for target in targets:
ninja target
retcode=$?
mv results.xml results-${target}.xml
<report the overall return code>
```
I want to use something like this Buildkite reporting plugin in CI, which needs to have all the results available:
https://buildkite.com/docs/agent/v3/cli-annotate#using-annotations-to-report-test-results
Modifying CI's build scripts for Windows and Linux is a lot of work. So
my changes instead make lit detect an existing result file and modify
the file name to find a new file to write to. Now you will get:
```
results.xml results.<tempfile generated value>.xml
```
This will work for all result file types since I'm doing it in the base
Report class. Now you've got separate files, it's easy to collect them
with `<path>/*.xml`.
Note that the `<tempfile generated value>` is not ordered.
Commit: f1ba8943c88ba2b53aaad407933dbb4b48b029d3
https://github.com/llvm/llvm-project/commit/f1ba8943c88ba2b53aaad407933dbb4b48b029d3
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/Symbols.cpp
M lld/COFF/Symbols.h
A lld/test/COFF/weak-antidep-chain.test
A lld/test/COFF/weak-antidep.test
Log Message:
-----------
[LLD][COFF] Support anti-dependency symbols (#112542)
Co-authored-by: Billy Laws <blaws05 at gmail.com>
Anti-dependency symbols are allowed to be duplicated, with the first
definition taking precedence. If a regular weak alias is present, it is
preferred over an anti-dependency definition. Chaining anti-dependencies
is not allowed.
Commit: 159f25301763215ffc49c3c3aa6cb8095a990b41
https://github.com/llvm/llvm-project/commit/159f25301763215ffc49c3c3aa6cb8095a990b41
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
A clang/test/AST/ByteCode/openmp.cpp
Log Message:
-----------
[clang][bytecode] Diagnose invalid declrefs differently if we've... (#113140)
... tried their initializer already. In that case, diagnose the
non-const initializer instead of the reference to a non-constexpr
variable later. This is used in a lot of openmp tests.
Commit: 95b4128c6a87e9b894aa75524e63be147cca790b
https://github.com/llvm/llvm-project/commit/95b4128c6a87e9b894aa75524e63be147cca790b
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InternalNames.h
M flang/lib/Optimizer/Support/InternalNames.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
A flang/test/Integration/debug-extra-global-2.f90
A flang/test/Integration/debug-extra-global.f90
A flang/test/Transforms/debug-extra-global.fir
Log Message:
-----------
[flang][debug] Don't generate debug for compiler-generated variables (#112423)
Flang generates many globals to handle derived types. There was a check
in debug info to filter them based on the information that their names
start with a period. This changed since PR#104859 where 'X' is being
used instead of '.'.
This PR fixes this issue by also adding 'X' in that list. As user
variables gets lower cased by the NameUniquer, there is no risk that
those will be filtered out. I added a test for that to be sure.
Commit: d906ac52ab8ee46090a6696f4ffb34c40ee6abb7
https://github.com/llvm/llvm-project/commit/d906ac52ab8ee46090a6696f4ffb34c40ee6abb7
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/mdouble.c
A clang/test/Sema/avr-size-align.c
M clang/test/Sema/unbounded-array-bounds.c
Log Message:
-----------
[clang][AVR] Fix basic type size/alignment values to match avr-gcc. (#111290)
Closes #102172
Commit: a18dd29077c84fc076a4ed431d9e815a3d0b6f24
https://github.com/llvm/llvm-project/commit/a18dd29077c84fc076a4ed431d9e815a3d0b6f24
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
Log Message:
-----------
[ConstantFolding] Set signed/implicitTrunc when handling GEP offsets
GEP offsets have sext_or_trunc semantics. We were already doing
this for the outer-most GEP, but not for the inner ones.
I believe one of the sanitizer buildbot failures was due to this,
but I did not manage to reproduce the issue or come up with a
test case. Usually the problematic case will already be folded
away due to index type canonicalization.
Commit: 25b58c877c851bed9c34362cd69bcd8d8bb65ac4
https://github.com/llvm/llvm-project/commit/25b58c877c851bed9c34362cd69bcd8d8bb65ac4
Author: Krasimir Georgiev <krasimir at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
bazelbuild: fix for commit 2ce10 (#113142)
bazelbuild: fix for
https://github.com/llvm/llvm-project/commit/2ce10f0491142863d3f21cd0adb312ab2cfed107.
No functional changes intended.
Commit: df02bcc81d5099d60c2ec037edf8eaeb66456319
https://github.com/llvm/llvm-project/commit/df02bcc81d5099d60c2ec037edf8eaeb66456319
Author: Krasimir Georgiev <krasimir at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
bazelbuild: fix for commit d80b9cf713fd (#113153)
Fix for
https://github.com/llvm/llvm-project/commit/d80b9cf713fd1698641c5b265de6b66618991476.
No functional changes intended.
Commit: c47df3e8c8f47bab8a8302757c50710e0e1c43fb
https://github.com/llvm/llvm-project/commit/c47df3e8c8f47bab8a8302757c50710e0e1c43fb
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/test/Shell/Recognizer/Inputs/verbose_trap-in-stl.cpp
Log Message:
-----------
[lldb][test] Make vector operator[] return T& to workaround Arm codegen issue
Since https://github.com/llvm/llvm-project/pull/109628 landed, this test
has been failing on 32-bit Arm.
This is due to a codegen problem (whether added or uncovered by the change,
not known) where the trap instruction is placed after the frame pointer
and link register are restored.
https://github.com/llvm/llvm-project/issues/113154
So the code was:
```
std::__1::vector<int>::operator[](unsigned int):
sub sp, sp, #8
str r0, [sp, #4]
str r1, [sp]
add sp, sp, #8
.inst 0xe7ffdefe
bx lr
```
When lldb saw the trap, the PC was inside operator[] but the frame
information actually pointed to g.
This bug only happens for leaf functions so adding a return type
works around it:
```
std::__1::vector<int>::operator[](unsigned int):
push {r11, lr}
mov r11, sp
sub sp, sp, #8
str r0, [sp, #4]
str r1, [sp]
mov sp, r11
pop {r11, lr}
.inst 0xe7ffdefe
bx lr
```
(and operator[] should return T& anyway)
Now the PC location and frame information should match and the
test passes.
Commit: 46dc91e7d9a1b6dd0144e628519d06954b7b4e53
https://github.com/llvm/llvm-project/commit/46dc91e7d9a1b6dd0144e628519d06954b7b4e53
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/include/clang/Basic/FileManager.h
M clang/include/clang/Basic/FileSystemStatCache.h
M clang/lib/Basic/FileManager.cpp
M clang/lib/Basic/FileSystemStatCache.cpp
M clang/lib/Lex/HeaderMap.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Serialization/ASTReader.cpp
A clang/test/Preprocessor/embed_zos.c
M llvm/include/llvm/Support/VirtualFileSystem.h
M llvm/lib/Support/VirtualFileSystem.cpp
Log Message:
-----------
[SystemZ][z/OS] Add new openFileForReadBinary function, and pass IsText parameter to getBufferForFile (#111723)
This patch adds an IsText parameter to the following getBufferForFile,
getBufferForFileImpl. We introduce a new virtual function
openFileForReadBinary which defaults to openFileForRead except in
RealFileSystem which uses the OF_None flag instead of OF_Text.
The default is set to OF_Text instead of OF_None, this change in value
does not affect any other platforms other than z/OS. Setting this
parameter correctly is required to open files on z/OS in the correct
encoding. The IsText parameter is based on the context of where we open
files, for example, in the ASTReader, HeaderMap requires that files
always be opened in binary even though they might be tagged as text.
Commit: 17ac10c28f0a3c078a82595787da7d855e581bf1
https://github.com/llvm/llvm-project/commit/17ac10c28f0a3c078a82595787da7d855e581bf1
Author: David Green <david.green at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll
Log Message:
-----------
Revert "[SLP]Initial non-power-of-2 support (but still whole register) for reductions"
This reverts commit 7f2e937469a8cec3fe977bf41ad2dfb9b4ce648a as it causes
regressions in the tests it modifies, and undoes what was added in #100653
(which itself was a fix for a previous regression).
Commit: 22e21bc1e796406c89e4a24fd81a1623ab2d7d85
https://github.com/llvm/llvm-project/commit/22e21bc1e796406c89e4a24fd81a1623ab2d7d85
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/utils/lit/lit/cl_arguments.py
Log Message:
-----------
[llvm][llvm-lit] Correct description of --use-unique-output-file-name
The initial version of this feature would use the output file name
if it could, but in switching to temp files I forgot to replicate that
behaviour.
What happens now is we always use a tempfile name and the output
path is a template for that. I think the current behaviour
still makes sense so I'm just correcting the documentation.
Commit: 6bac41496eb24c80aa659008d08220355a617c49
https://github.com/llvm/llvm-project/commit/6bac41496eb24c80aa659008d08220355a617c49
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
Log Message:
-----------
[RISCV][GISEL] Legalize G_INSERT_SUBVECTOR (#108859)
This code is heavily based on the SelectionDAG lowerINSERT_SUBVECTOR
code.
Commit: 08330dba923c6293b71c85a9f27153c630adc968
https://github.com/llvm/llvm-project/commit/08330dba923c6293b71c85a9f27153c630adc968
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/utils/lit/lit/cl_arguments.py
Log Message:
-----------
[llvm][llvm-lit] Fix missing word in --use-unique-output-file-name help
Fixes 22e21bc1e796406c89e4a24fd81a1623ab2d7d85.
Commit: e26d9070d3eaee587b3ef0da6d12200a5b994765
https://github.com/llvm/llvm-project/commit/e26d9070d3eaee587b3ef0da6d12200a5b994765
Author: Nathan Gauër <brioche at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/Transforms/Utils.h
M llvm/lib/Transforms/Scalar/Reg2Mem.cpp
Log Message:
-----------
[Reg2Mem] Add legacy pass wrapping Reg2Mem (#111024)
The SPIR-V backend will need to use Reg2Mem, hence this pass needs to be
wrapped to be used with the legacy pass manager.
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 89d8449a2900123c2e9bd7a11315381b2b70c155
https://github.com/llvm/llvm-project/commit/89d8449a2900123c2e9bd7a11315381b2b70c155
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC] Fix LLJIT's __cxa_atexit declaration for clang-repl. (#113141)
Add sign extension on i32 return value.
Commit: ecfeacd152f07cf8aea210f63415e3e48b05ab22
https://github.com/llvm/llvm-project/commit/ecfeacd152f07cf8aea210f63415e3e48b05ab22
Author: David Green <david.green at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] Convert aarch64_neon_sqxtn to ISD::TRUNCATE_SSAT_S and replace tablegen patterns
This lowers the aarch64_neon_sqxtn intrinsics to the new TRUNCATE_SSAT_S ISD
nodes, performing the same for sqxtun and uqxtn. This allows us to clean up the
tablegen patterns a little and in a future commit add combines for sqxtn.
Commit: c44860c8d2582abd88794267b4fa0fa953bbef80
https://github.com/llvm/llvm-project/commit/c44860c8d2582abd88794267b4fa0fa953bbef80
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[Flang][OpenMP] Disable lowering of omp.simd reductions in composites (#112686)
Currently, the `omp.simd` operation is ignored during MLIR to LLVM IR
translation when it takes part in a composite construct. One consequence
of this limitation is that any entry block arguments defined by that
operation will trigger a compiler crash if they are used anywhere, as
they are not bound to an LLVM IR value.
A previous PR introducing support for the `reduction` clause resulted in
the creation and use of entry block arguments attached to the `omp.simd`
operation, causing compiler crashes on 'do simd reduction(...)'
constructs.
This patch disables Flang lowering of simd reductions in 'do simd'
constructs to avoid triggering these errors while translation to LLVM IR
is still incomplete.
Commit: 5c9c281c251402fd65bb01717112cf22019ee409
https://github.com/llvm/llvm-project/commit/5c9c281c251402fd65bb01717112cf22019ee409
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h
M llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
Log Message:
-----------
[DebugInfo] Use heterogenous lookups with std::map (NFC) (#113118)
Commit: 61a286ac0817671ad09a505303b7a3a446798316
https://github.com/llvm/llvm-project/commit/61a286ac0817671ad09a505303b7a3a446798316
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
Log Message:
-----------
[tools] Don't call StringRef::str() when calling StringMap::find (NFC) (#113119)
StringMap::find takes StringRef. We don't need to create an instance
of std::string from StringRef only to convert it right back to
StringRef.
Commit: 1bf1e92c72ec9086ab24103cf968e115b7248101
https://github.com/llvm/llvm-project/commit/1bf1e92c72ec9086ab24103cf968e115b7248101
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
Log Message:
-----------
[lldb] Avoid repeated map lookups (NFC) (#113121)
Commit: af6e1881e0791ac1ee611b62a3d12d9fb03ca142
https://github.com/llvm/llvm-project/commit/af6e1881e0791ac1ee611b62a3d12d9fb03ca142
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
Log Message:
-----------
[mlir] Avoid repeated map lookups (NFC) (#113122)
Commit: e2074c60bb3982cd8afb6408670332ea27da6383
https://github.com/llvm/llvm-project/commit/e2074c60bb3982cd8afb6408670332ea27da6383
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
Log Message:
-----------
[AArch64] Use implicitTrunc in isBitfieldDstMask() (NFC)
This code intentionally discards the high bits, so set
implicitTrunc=true. This is currently NFC but will enable an
APInt assertion in the future.
Commit: f0312d962d0510d613a5ad1aec0f0e44d4f124c0
https://github.com/llvm/llvm-project/commit/f0312d962d0510d613a5ad1aec0f0e44d4f124c0
Author: Andrea Faulds <andrea.faulds at amd.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/test/lib/Pass/CMakeLists.txt
A mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/mlir-spirv-cpu-runner/double.mlir
M mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
Log Message:
-----------
[mlir][mlir-spirv-cpu-runner] Move MLIR pass pipeline to mlir-opt (#111575)
Adds a new mlir-opt test-only pass, -test-spirv-cpu-runner-pipeline,
which runs the set of MLIR passes needed for the mlir-spirv-cpu-runner,
and removes them from the runner. The tests are changed to invoke
mlir-opt with this flag before running the runner. The eventual goal is
to move all host/device code generation steps out of the runner, like
with some of the other runners.
Commit: f2302ed3d0f84ca867a3e664ed65bc89e52ee670
https://github.com/llvm/llvm-project/commit/f2302ed3d0f84ca867a3e664ed65bc89e52ee670
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
Log Message:
-----------
[RISCV][GISEL] Fix operand on RISCV::G_VMV_V_V_VL
6bac41496eb24c80aa659008d08220355a617c49 added this opcode with the wrong
number of operands. It didn't fail on check-llvm for me or on pre-commit CI,
but once committed we got buildbot failures. This patch fixes the definition
of the instruction and fixes the failing test.
Commit: bd861d0e690cfd05184d86e954289cccfec97e92
https://github.com/llvm/llvm-project/commit/bd861d0e690cfd05184d86e954289cccfec97e92
Author: David Green <david.green at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/qshrn.ll
Log Message:
-----------
[AArch64] Add some basic patterns for qshrn.
With the truncssat nodes these are relatively simple tablegen patterns to add.
The existing intrinsics are converted to shift+truncsat to they can lower using
the new patterns.
Fixes #112925.
Commit: 1dfdbf716112627dea5e79f7f4f1e1e9335ee9df
https://github.com/llvm/llvm-project/commit/1dfdbf716112627dea5e79f7f4f1e1e9335ee9df
Author: Boaz Brickner <brickner at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/test/CXX/drs/cwg9xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add covariance tests that make sure we return an error when return value is different in pointer / lvalue ref / rvalue ref (#112853)
Per https://cplusplus.github.io/CWG/issues/960.html.
Commit: 67ff5ba9af9754261abe11d762af11532a816126
https://github.com/llvm/llvm-project/commit/67ff5ba9af9754261abe11d762af11532a816126
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/MC/AArch64/LSFE/directive-arch-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension.s
A llvm/test/MC/AArch64/LSFE/directive-cpu-negative.s
A llvm/test/MC/AArch64/LSFE/directive-cpu.s
A llvm/test/MC/AArch64/LSFE/ldfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfadd.s
A llvm/test/MC/AArch64/LSFE/ldfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmax.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm.s
A llvm/test/MC/AArch64/LSFE/ldfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmin.s
A llvm/test/MC/AArch64/LSFE/ldfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfminnm.s
A llvm/test/MC/AArch64/LSFE/stfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfadd.s
A llvm/test/MC/AArch64/LSFE/stfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmax.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm.s
A llvm/test/MC/AArch64/LSFE/stfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmin.s
A llvm/test/MC/AArch64/LSFE/stfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfminnm.s
Log Message:
-----------
[AArch64] Add assembly/disaasembly of atomic ld/st (#112892)
This patch adds assembly/disassembly for the following instructions:
ldfadd{a,al,l,}, ldbfadd{a,al,l,}
ldfmax{a,al,l,}, ldbfmax{a,al,l,}
ldfmaxnm{a,al,l,}, ldbfmaxnm{a,al,l,}
ldfmin{a,al,l,}, ldbfmin{a,al,l,}
ldfminnm{a,al,l,} ldbfminnm{a,al,l,}
stfadd{l,}, stbfadd{l,}
stfmax{l,}, stbfmax{l,}
stfmaxnm{l,}, stbfmaxnm{l,}
stfmin{l,}, stbfmin{l,}
stfminnm{l,}, stbfminnm{l,}
According to [1]
[1]https://developer.arm.com/documentation/ddi0602
Co-authored-by: Spencer Abson
[spencer.abson at arm.com](mailto:spencer.abson at arm.com)
Co-authored-by: Caroline Concatto
[caroline.concatto at arm.com](mailto:caroline.concatto at arm.com)
Commit: a2ba438f3e5635e368333213914c7452a6a6a2da
https://github.com/llvm/llvm-project/commit/a2ba438f3e5635e368333213914c7452a6a6a2da
Author: XChy <xxs_chy at outlook.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
Log Message:
-----------
[InstCombine] Preserve the flag from RHS only if the `and` is bitwise (#113164)
Fixes #113123
Alive proof: https://alive2.llvm.org/ce/z/hnqeLC
Commit: 1e07c4800cf46ac9e4748b664cb58cbd48acb918
https://github.com/llvm/llvm-project/commit/1e07c4800cf46ac9e4748b664cb58cbd48acb918
Author: Chris Apple <cja-private at pm.me>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M compiler-rt/lib/rtsan/CMakeLists.txt
R compiler-rt/lib/rtsan/rtsan_interceptors.cpp
A compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
R compiler-rt/lib/rtsan/tests/rtsan_test_interceptors.cpp
A compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
Log Message:
-----------
[rtsan][NFC] Rename *interceptors.cpp to *interceptors_posix.cpp (#112935)
Done in preparation of exploring rtsan on windows.
Commit: 4679583181a9032b4f7c6476c7a1bfefe5724b47
https://github.com/llvm/llvm-project/commit/4679583181a9032b4f7c6476c7a1bfefe5724b47
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Log Message:
-----------
[LLVM][AArch64] Add register classes for Armv9.6 assembly (#111717)
Add new register classes/operands and their encoder/decoder behaviour
required for the new Armv9.6 instructions (see
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension).
This work is the basis ofthe 2024 Armv9.6 architecture update effort for
SME.
Co-authored-by: Caroline Concatto caroline.concatto at arm.com
Co-authored-by: Marian Lukac marian.lukac at arm.com
Co-authored-by: Momchil Velikov momchil.velikov at arm.com
Commit: e7302319b52e3d231216d54d10622b0698928a96
https://github.com/llvm/llvm-project/commit/e7302319b52e3d231216d54d10622b0698928a96
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/test/lib/Pass/CMakeLists.txt
Log Message:
-----------
[mlir] Fix shared build. NFC
Commit: 17e9752267ed9c81c8da87f3a6d0e01f130b0d04
https://github.com/llvm/llvm-project/commit/17e9752267ed9c81c8da87f3a6d0e01f130b0d04
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M mlir/test/lib/Pass/CMakeLists.txt
R mlir/test/lib/Pass/TestSPIRVCPURunnerPipeline.cpp
M mlir/test/mlir-spirv-cpu-runner/double.mlir
M mlir/test/mlir-spirv-cpu-runner/simple_add.mlir
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
Log Message:
-----------
Revert "[mlir][mlir-spirv-cpu-runner] Move MLIR pass pipeline to mlir-opt" (#113176)
Reverts llvm/llvm-project#111575
This caused build failures:
https://lab.llvm.org/buildbot/#/builders/138/builds/5244
Commit: c5ca1b8626db71fa7ac5d851fa3a0710641136ff
https://github.com/llvm/llvm-project/commit/c5ca1b8626db71fa7ac5d851fa3a0710641136ff
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/test/CodeGen/PowerPC/sat-add.ll
A llvm/test/CodeGen/PowerPC/uaddo-32.ll
A llvm/test/CodeGen/PowerPC/uaddo-64.ll
Log Message:
-----------
[PPC] Add custom lowering for uaddo (#110137)
Improve the codegen for uaddo node for i64 in 64-bit mode and i32 in
32-bit mode by custom lowering.
Commit: 900b6369e2f5fbc229371a142fdcd28b5280dbc0
https://github.com/llvm/llvm-project/commit/900b6369e2f5fbc229371a142fdcd28b5280dbc0
Author: Jake Egan <jake.egan at ibm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/log1p.ll
Log Message:
-----------
[AIX][test] XFAIL constant folding log1p test
Test added by commit 47a6da2d4dc7d996eb2678243ac566822d59e483 fails on the AIX bot. So XFAIL for now to investigate further.
Commit: 120e42d3135f558b5e0a73da1c6484571eeff941
https://github.com/llvm/llvm-project/commit/120e42d3135f558b5e0a73da1c6484571eeff941
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Improve metadata cleanup in LTO backend (#113039)
Previously we were attempting to remove the memprof-related metadata
when iterating through instructions in the LTO backend. However, we
missed some as there are a number of cases where we skip instructions,
or even entire functions. Simplify the cleanup and ensure all is removed
by doing a full sweep over all instructions after completing cloning.
This is largely NFC except with -memprof-report-hinted-sizes enabled,
because we were propagating and simplifying the metadata after inlining
in the LTO backend, which caused some stray messages as metadata was
re-converted to attributes.
Commit: 8417f6af54c8f6dcf5893ab1352b50bf33c5a1ba
https://github.com/llvm/llvm-project/commit/8417f6af54c8f6dcf5893ab1352b50bf33c5a1ba
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[win/asan] Fix instruction size for 44 0f b6 1a
movzx r11d,BYTE PTR [rdx]
is four bytes long.
Follow-up to #111638
Commit: 42ba452aa94e4da277842d8990ad958a6256e558
https://github.com/llvm/llvm-project/commit/42ba452aa94e4da277842d8990ad958a6256e558
Author: Spencer Abson <Spencer.Abson at arm.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Log Message:
-----------
[NFC] Fix -WError for unused Encode/Decode ZK methods
Remove the unused functions and register classes from the change below
https://github.com/llvm/llvm-project/commit/4679583181a9032b4f7c6476c7a1bfefe5724b47
Commit: 9e03920cbf946e7ba282e99213707643a23ae5fb
https://github.com/llvm/llvm-project/commit/9e03920cbf946e7ba282e99213707643a23ae5fb
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/root-gather-reused-scalar.ll
Log Message:
-----------
[SLP]Ignore root gather node, when searching for reuses
Root gather/buildvector node should be ignored when SLP vectorizer tries
to find matching gather nodes, vectorized earlier. This node is
definitely the last one in the pipeline and it does not have users. It
may cause the compiler crash
Fixes #113143
Commit: 54c93aabec965469fe7db1f4391a190e3d640feb
https://github.com/llvm/llvm-project/commit/54c93aabec965469fe7db1f4391a190e3d640feb
Author: vporpo <vporpodas at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
Log Message:
-----------
[SandboxVec][Legality] Scaffolding for Legality (#112623)
This patch adds a LegalityResultWithReason class for describing the
reason why legality decided not to vectorize the code.
Commit: fc59f2cc0f191bb7a0706dfb65e3e46fef69f466
https://github.com/llvm/llvm-project/commit/fc59f2cc0f191bb7a0706dfb65e3e46fef69f466
Author: RolandF77 <55763885+RolandF77 at users.noreply.github.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
A llvm/test/CodeGen/PowerPC/const-stov.ll
M llvm/test/CodeGen/PowerPC/load-and-splat.ll
M llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll
M llvm/test/CodeGen/PowerPC/ppc-32bit-build-vector.ll
Log Message:
-----------
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
Special case small int constant in the PPC custom lowering of
scalar_to_vector.
Commit: f1e455ed51be4f53462db87aa5d64dbd830e5de2
https://github.com/llvm/llvm-project/commit/f1e455ed51be4f53462db87aa5d64dbd830e5de2
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[NFC][Sema][OpenMP] Fix free-nonheap-object warning (#112942)
This is one of the many PRs to fix errors with LLVM_ENABLE_WERROR=on.
Built by GCC 11.
Fix warning
In destructor ‘llvm::APInt::~APInt()’,
inlined from ‘llvm::APInt::~APInt()’ at
llvm-project/llvm/include/llvm/ADT/APInt.h:190:3,
inlined from ‘llvm::APSInt::~APSInt()’ at
llvm-project/llvm/include/llvm/ADT/APSInt.h:23:21,
inlined from ‘bool
checkOMPArraySectionConstantForReduction(clang::ASTContext&, const
clang::ArraySectionExpr*, bool&, llvm::SmallVectorImpl<llvm::APSInt>&)’
at llvm-project/clang/lib/Sema/SemaOpenMP.cpp:18357:45,
inlined from ‘bool actOnOMPReductionKindClause(clang::Sema&,
{anonymous}::DSAStackTy*, clang::OpenMPClauseKind,
llvm::ArrayRef<clang::Expr*>, clang::SourceLocation,
clang::SourceLocation, clang::SourceLocation, clang::SourceLocation,
clang::CXXScopeSpec&, const clang::DeclarationNameInfo&,
llvm::ArrayRef<clang::Expr*>, {anonymous}::ReductionData&)’ at
llvm-project/clang/lib/Sema/SemaOpenMP.cpp:18715:68:
llvm-project/llvm/include/llvm/ADT/APInt.h:192:18: error: ‘void operator
delete [](void*)’ called on a pointer to an unallocated object ‘1’
[-Werror=free-nonheap-object]
192 | delete[] U.pVal;
| ^~~~
Commit: d4630ae5ed678e50f4758d0fb7a6875494f690e5
https://github.com/llvm/llvm-project/commit/d4630ae5ed678e50f4758d0fb7a6875494f690e5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
Log Message:
-----------
[Vectorize] Fix a warning
This patch fixes:
llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h:85:16:
error: private field 'Reason' is not used
[-Werror,-Wunused-private-field]
Commit: 006fb0904d8e549476342de4b749792f73b3af85
https://github.com/llvm/llvm-project/commit/006fb0904d8e549476342de4b749792f73b3af85
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
Log Message:
-----------
[gn build] Port 54c93aabec96
Commit: 3277c7cd28154e33637a168acb26cea7ac1f7fff
https://github.com/llvm/llvm-project/commit/3277c7cd28154e33637a168acb26cea7ac1f7fff
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
Log Message:
-----------
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.
Commit: ac9ee618572537bcd77c58899aaab1d41dbad206
https://github.com/llvm/llvm-project/commit/ac9ee618572537bcd77c58899aaab1d41dbad206
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeDataValues.cpp
M mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
[acc] Improve LegalizeDataValues pass to handle data constructs (#112990)
Renames LegalizeData to LegalizeDataValues since this pass fixes up SSA
values. LegalizeData suggested that it fixed data mapping.
This change also adds support to fix up ssa values for data clause
operations. Effectively, compute regions within a data region use the
ssa values from data operations also. The ssa values within data regions
but not within compute regions are not updated.
This change is to support the requirement in the OpenACC spec which
notes that a visible data clause is not just one on the current compute
construct but on the lexically containing data construct or visible
declare directive.
Commit: dcbf2c2ca078367fcd84feae9a51226b9761117a
https://github.com/llvm/llvm-project/commit/dcbf2c2ca078367fcd84feae9a51226b9761117a
Author: Farzon Lotfi <1802579+farzonl at users.noreply.github.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Transforms/Scalar/Scalarizer.cpp
A llvm/test/CodeGen/DirectX/split-double.ll
A llvm/test/Transforms/Scalarizer/frexp.ll
Log Message:
-----------
[Scalarizer][DirectX] support structs return types (#111569)
Based on this RFC:
https://discourse.llvm.org/t/rfc-allow-the-scalarizer-pass-to-scalarize-vectors-returned-in-structs/82306
LLVM intrinsics do not support out params. To get around this limitation
implementers will make intrinsics return structs to capture a return
type and an out param. This implementation detail should not impact
scalarization since these cases should be elementwise operations.
## Three changes are needed.
- The CallInst visitor needs to be updated to handle Structs
- A new visitor is needed for `ExtractValue` instructions
- finsh needs to be update to handle structs so that insert elements are
properly propogated.
## Testing changes
- Add support for `llvm.frexp`
- Add support for `llvm.dx.splitdouble`
fixes https://github.com/llvm/llvm-project/issues/111437
Commit: 7eb8238a32516008476b717bc6a2be8c59f7f535
https://github.com/llvm/llvm-project/commit/7eb8238a32516008476b717bc6a2be8c59f7f535
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/TableGen/x86-fold-tables.td
Log Message:
-----------
[TableGen] Handle Windows line endings in x86-fold-tables.td test (#112997)
The x86-fold-tables.td has been failing for me and [in
CI](https://buildkite.com/llvm-project/github-pull-requests/builds/111277#0192a122-c5c9-4e4e-bc5b-7532fec99ae4)
if Git happens to decide to check out the baseline file with Windows
line endings.
This fix for this is to add the `--strip-trailing-cr` option to diff to
normalize the line endings before comparing them.
Commit: 8ae39c8e34de2d24c46827b324c76bac845c18b0
https://github.com/llvm/llvm-project/commit/8ae39c8e34de2d24c46827b324c76bac845c18b0
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
Log Message:
-----------
[MC] Fix llvm-mc unterminated string constants warning for Windows (#112995)
#98060 introduced a warning for unterminated string constants, however
it was only checking for `\n` which means that it produced strange
results on Windows (always blaming column 1) including having the
[associated test
fail](https://buildkite.com/llvm-project/github-pull-requests/builds/111277#0192a122-c5c9-4e4e-bc5b-7532fec99ae4)
if Git happened to use Windows newlines when creating the file.
This fix for this is to detect both `\r` and `\n`, but don't double-warn
for Windows newlines.
Commit: 766bd6f4d05a4b52892be4f1b740e67053a22ee6
https://github.com/llvm/llvm-project/commit/766bd6f4d05a4b52892be4f1b740e67053a22ee6
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
Log Message:
-----------
[AMDGPU] Avoid repeated map lookups (NFC) (#112819)
Commit: eaa7b385368fa7e3dad9b95411d04be55e71494e
https://github.com/llvm/llvm-project/commit/eaa7b385368fa7e3dad9b95411d04be55e71494e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
Log Message:
-----------
[Transforms] Avoid repeated hash lookups (NFC) (#113120)
Commit: 30a402833f50b14148c8b963f3ffaaeaeea5fd78
https://github.com/llvm/llvm-project/commit/30a402833f50b14148c8b963f3ffaaeaeea5fd78
Author: Augusto Noronha <anoronha at apple.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/include/lldb/Symbol/TypeSystem.h
Log Message:
-----------
[lldb][NFC] Fix doxygen comment on top of GetMangledTypeName
Commit: ab07fc832009b678c0b24392ad7e02a8e5dd3932
https://github.com/llvm/llvm-project/commit/ab07fc832009b678c0b24392ad7e02a8e5dd3932
Author: Yijia Gu <yijiagu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] add missing dep in OpenAccTransforms
Commit: 2c331b35712e0fad93cf804674196b7c0e47ebd9
https://github.com/llvm/llvm-project/commit/2c331b35712e0fad93cf804674196b7c0e47ebd9
Author: Yijia Gu <yijiagu at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] remove tab blank in OpenAccTransforms
Commit: 4de708e32e31ac32b924dfeb020086636700c0f7
https://github.com/llvm/llvm-project/commit/4de708e32e31ac32b924dfeb020086636700c0f7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj
R lldb/tools/debugserver/source/MacOSX/stack_logging.h
Log Message:
-----------
[lldb] Remove stack_logging.h (#112987)
This file is covered under the Apple open source license rather than the
LLVM license. Presumably this was an oversight, but it doesn't really
matter as this file is unused. Remove it altogether.
Commit: ed5072ee28809abf0f140ca15df549a418bb5c69
https://github.com/llvm/llvm-project/commit/ed5072ee28809abf0f140ca15df549a418bb5c69
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M lld/test/MachO/icf-safe-thunks-dwarf.ll
M lld/test/MachO/icf-safe-thunks.ll
Log Message:
-----------
[NFC][lld-macho] Generate test bodies for icf-safe-thunk tests (#111927)
Autogenerate `.ll` code from cpp code in some `-icf-safe-thunk` tests
using `update_test_body.py`
```
PATH=build/bin:$PATH llvm/utils/update_test_body.py lld/test/MachO/icf-safe-thunks.ll lld/test/MachO/icf-safe-thunks-dwarf.ll
```
https://llvm.org/docs/TestingGuide.html#elaborated-tests
I recently became aware of this tool and I wanted to practice using it.
This also allows to remove the custom instructions to generate the `.ll`
code.
Commit: 59528bbc73644f7c9e08406cf61a21b5dd8fe3b8
https://github.com/llvm/llvm-project/commit/59528bbc73644f7c9e08406cf61a21b5dd8fe3b8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
Log Message:
-----------
[nfc][msan] Reorder flags in RUN: (#113196)
Commit: cafeacff2c6367a229aa8b65be99835177f5c3be
https://github.com/llvm/llvm-project/commit/cafeacff2c6367a229aa8b65be99835177f5c3be
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
Log Message:
-----------
[nfc][msan] Remove RUN: duplicates (#113197)
Commit: 084ae5ad2d09b62ca6b0d493d89b532fcf0e7dd0
https://github.com/llvm/llvm-project/commit/084ae5ad2d09b62ca6b0d493d89b532fcf0e7dd0
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-21 (Mon, 21 Oct 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/stage1.Dockerfile
M clang-tools-extra/clangd/Config.h
M clang-tools-extra/clangd/ConfigCompile.cpp
M clang-tools-extra/clangd/ConfigFragment.h
M clang-tools-extra/clangd/ConfigYAML.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang/docs/analyzer/user-docs/CommandLineUsage.rst
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/ASTMatchers/ASTMatchersMacros.h
M clang/include/clang/Basic/FileManager.h
M clang/include/clang/Basic/FileSystemStatCache.h
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ExprCXX.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/Basic/FileSystemStatCache.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/lib/Lex/HeaderMap.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Tooling/Inclusions/HeaderIncludes.cpp
M clang/test/AST/ByteCode/complex.cpp
M clang/test/AST/ByteCode/cxx98.cpp
A clang/test/AST/ByteCode/openmp.cpp
M clang/test/CXX/drs/cwg9xx.cpp
M clang/test/CodeGen/attr-target-clones-riscv.c
M clang/test/CodeGen/attr-target-version-riscv.c
M clang/test/CodeGen/cx-complex-range.c
M clang/test/CodeGen/mdouble.c
M clang/test/CodeGenCUDA/bf16.cu
M clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
M clang/test/CodeGenCXX/attr-target-version-riscv.cpp
M clang/test/CoverageMapping/branch-constfolded.cpp
M clang/test/CoverageMapping/if.cpp
M clang/test/CoverageMapping/macro-expansion.c
M clang/test/CoverageMapping/mcdc-scratch-space.c
M clang/test/CoverageMapping/mcdc-system-headers.cpp
M clang/test/CoverageMapping/switch.cpp
M clang/test/CoverageMapping/switchmacro.c
A clang/test/Format/dry-run-warning.cpp
A clang/test/Preprocessor/embed_zos.c
A clang/test/Sema/avr-size-align.c
M clang/test/Sema/unbounded-array-bounds.c
M clang/test/SemaCXX/attr-target-clones-riscv.cpp
M clang/test/SemaCXX/attr-target-version-riscv.cpp
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-format/clang-format.el
M clang/www/cxx_dr_status.html
M compiler-rt/lib/hwasan/CMakeLists.txt
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/rtsan/CMakeLists.txt
R compiler-rt/lib/rtsan/rtsan_interceptors.cpp
A compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/rtsan/tests/CMakeLists.txt
R compiler-rt/lib/rtsan/tests/rtsan_test_interceptors.cpp
A compiler-rt/lib/rtsan/tests/rtsan_test_interceptors_posix.cpp
M compiler-rt/test/asan/TestCases/Windows/delay_dbghelp.cpp
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
A flang/include/flang/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.h
M flang/include/flang/Optimizer/OpenMP/Passes.td
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/include/flang/Optimizer/Support/InternalNames.h
A flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Dialect/CUF/CMakeLists.txt
A flang/lib/Optimizer/Dialect/CUF/CUFToLLVMIRTranslation.cpp
M flang/lib/Optimizer/OpenMP/CMakeLists.txt
A flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Support/InternalNames.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CufOpConversion.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/runtime/CUDA/CMakeLists.txt
A flang/runtime/CUDA/registration.cpp
M flang/test/Fir/CUDA/cuda-register-func.fir
M flang/test/Fir/OpenACC/legalize-data.fir
M flang/test/Fir/cuf-invalid.fir
A flang/test/Integration/debug-extra-global-2.f90
A flang/test/Integration/debug-extra-global.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
A flang/test/Semantics/OpenMP/atomic06-empty.f90
A flang/test/Semantics/OpenMP/declare-simd-empty.f90
A flang/test/Semantics/OpenMP/threadprivate08-empty.f90
A flang/test/Transforms/debug-extra-global.fir
A flang/test/Transforms/omp-maps-for-privatized-symbols.fir
M libc/hdr/stdio_overlay.h
M libc/hdr/wchar_overlay.h
M libc/newhdrgen/yaml/math.yaml
M libc/src/string/CMakeLists.txt
M libc/src/string/strcat.h
M libc/src/string/strcpy.h
M libc/src/string/strdup.h
M libc/src/string/strlcat.h
M libc/src/string/strlcpy.h
M libc/src/string/strlen.h
M libc/src/string/strncat.h
M libc/src/string/strndup.h
M libcxx/include/CMakeLists.txt
M libcxx/include/__iterator/reverse_iterator.h
M libcxx/include/clocale
M libcxx/include/cstdint
R libcxx/include/locale.h
M libcxx/include/module.modulemap
R libcxx/include/stdint.h
M libcxx/test/libcxx/depr/depr.c.headers/extern_c.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/greater-equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/greater.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/less-equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/less.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cmp/not-equal.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/assign.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/ctor.default.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/ctor.iter.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.cons/ctor.reverse_iterator.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.conv/base.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.elem/arrow.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.elem/bracket.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.elem/dereference.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/decrement-assign.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/increment-assign.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/minus.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/plus.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/postdecrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/postincrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/predecrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nav/preincrement.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/make_reverse_iterator.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/minus.pass.cpp
M libcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iter.nonmember/plus.pass.cpp
M libcxx/utils/libcxx/header_information.py
M libunwind/src/UnwindCursor.hpp
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/Symbols.cpp
M lld/COFF/Symbols.h
M lld/ELF/AArch64ErrataFix.cpp
M lld/ELF/ARMErrataFix.cpp
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/AVR.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Arch/SystemZ.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Driver.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MapFile.cpp
M lld/ELF/OutputSections.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Symbols.cpp
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Thunks.cpp
M lld/ELF/Writer.cpp
A lld/test/COFF/weak-antidep-chain.test
A lld/test/COFF/weak-antidep.test
M lld/test/MachO/icf-safe-thunks-dwarf.ll
M lld/test/MachO/icf-safe-thunks.ll
M lldb/include/lldb/Core/Module.h
M lldb/include/lldb/Symbol/CompilerType.h
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/include/lldb/Target/Language.h
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Core/DataFileCache.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Interpreter/Options.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangASTImporter.cpp
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
M lldb/source/Plugins/Process/elf-core/CMakeLists.txt
A lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.cpp
A lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
M lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/PDB/SymbolFilePDB.cpp
M lldb/source/Symbol/CompilerType.cpp
M lldb/source/Symbol/TypeSystem.cpp
M lldb/source/Target/ThreadPlanStepOverRange.cpp
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
A lldb/test/API/functionalities/postmortem/elf-core/linux-loongarch64.core
A lldb/test/API/functionalities/postmortem/elf-core/linux-loongarch64.out
M lldb/test/Shell/Recognizer/Inputs/verbose_trap-in-stl.cpp
A lldb/test/Shell/SymbolFile/DWARF/TestDedupWarnings.test
M lldb/tools/debugserver/debugserver.xcodeproj/project.pbxproj
R lldb/tools/debugserver/source/MacOSX/stack_logging.h
M llvm/docs/CommandGuide/llvm-cxxfilt.rst
M llvm/include/llvm/Analysis/TargetLibraryInfo.def
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/InitializePasses.h
M llvm/include/llvm/LinkAllPasses.h
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/Support/VirtualFileSystem.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Transforms/Utils.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/Reg2Mem.cpp
M llvm/lib/Transforms/Scalar/Scalarizer.cpp
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-shifts-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/qshrn.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
M llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-nondeterminism.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/fma-combine.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.gfx10.mir
M llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir
M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp32.ll
M llvm/test/CodeGen/AMDGPU/fp16_to_fp64.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
M llvm/test/CodeGen/AMDGPU/imm16.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill.mir
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
M llvm/test/CodeGen/AMDGPU/mad.u16.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/madak.ll
M llvm/test/CodeGen/AMDGPU/match-perm-extract-vector-elt-bug.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
A llvm/test/CodeGen/ARM/fmuladd-soft-float.ll
A llvm/test/CodeGen/ARM/pr112710.ll
A llvm/test/CodeGen/DirectX/split-double.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
A llvm/test/CodeGen/Mips/fmuladd-soft-float.ll
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/addr-mode.ll
M llvm/test/CodeGen/NVPTX/aggregate-return.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
M llvm/test/CodeGen/NVPTX/chain-different-as.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-mad.ll
M llvm/test/CodeGen/NVPTX/compute-ptx-value-vts.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/dot-product.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i128-param.ll
M llvm/test/CodeGen/NVPTX/i128-retval.ll
M llvm/test/CodeGen/NVPTX/i128-struct.ll
M llvm/test/CodeGen/NVPTX/i128.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/jump-table.ll
M llvm/test/CodeGen/NVPTX/ldparam-v4.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-alloca.ll
M llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll
M llvm/test/CodeGen/NVPTX/lower-args.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/mulhi-intrins.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/param-load-store.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/param-vectorize-device.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
M llvm/test/CodeGen/NVPTX/sad-intrins.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/store-undef.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/tid-range.ll
M llvm/test/CodeGen/NVPTX/unaligned-param-load-store.ll
M llvm/test/CodeGen/NVPTX/unfold-masked-merge-vector-variablemask.ll
M llvm/test/CodeGen/NVPTX/vaargs.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vec-param-load.ll
M llvm/test/CodeGen/NVPTX/vector-args.ll
M llvm/test/CodeGen/NVPTX/vector-call.ll
M llvm/test/CodeGen/NVPTX/vector-returns.ll
M llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll
M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
A llvm/test/CodeGen/PowerPC/const-stov.ll
M llvm/test/CodeGen/PowerPC/load-and-splat.ll
M llvm/test/CodeGen/PowerPC/p10-splatImm32-undef.ll
M llvm/test/CodeGen/PowerPC/ppc-32bit-build-vector.ll
M llvm/test/CodeGen/PowerPC/sat-add.ll
A llvm/test/CodeGen/PowerPC/uaddo-32.ll
A llvm/test/CodeGen/PowerPC/uaddo-64.ll
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-insert-subvector.mir
A llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll
A llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll
A llvm/test/CodeGen/X86/fmuladd-soft-float.ll
M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
A llvm/test/MC/AArch64/LSFE/directive-arch-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension-negative.s
A llvm/test/MC/AArch64/LSFE/directive-arch_extension.s
A llvm/test/MC/AArch64/LSFE/directive-cpu-negative.s
A llvm/test/MC/AArch64/LSFE/directive-cpu.s
A llvm/test/MC/AArch64/LSFE/ldfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfadd.s
A llvm/test/MC/AArch64/LSFE/ldfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmax.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmaxnm.s
A llvm/test/MC/AArch64/LSFE/ldfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfmin.s
A llvm/test/MC/AArch64/LSFE/ldfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/ldfminnm.s
A llvm/test/MC/AArch64/LSFE/stfadd-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfadd.s
A llvm/test/MC/AArch64/LSFE/stfmax-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmax.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmaxnm.s
A llvm/test/MC/AArch64/LSFE/stfmin-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfmin.s
A llvm/test/MC/AArch64/LSFE/stfminnm-diagnostics.s
A llvm/test/MC/AArch64/LSFE/stfminnm.s
M llvm/test/TableGen/x86-fold-tables.td
M llvm/test/ThinLTO/X86/memprof-icp.ll
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
M llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
A llvm/test/Transforms/InstCombine/ilogb.ll
M llvm/test/Transforms/InstCombine/log1p.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
A llvm/test/Transforms/SLPVectorizer/X86/root-gather-reused-scalar.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll
A llvm/test/Transforms/Scalarizer/frexp.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
M llvm/test/tools/llvm-cov/branch-c-general.test
A llvm/test/tools/llvm-cxxfilt/quote.test
M llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
M llvm/tools/llvm-cov/CoverageExporterJson.cpp
M llvm/tools/llvm-cov/CoverageExporterLcov.cpp
M llvm/tools/llvm-cov/CoverageSummaryInfo.cpp
M llvm/tools/llvm-cov/SourceCoverageViewHTML.cpp
M llvm/tools/llvm-cov/SourceCoverageViewText.cpp
M llvm/tools/llvm-cxxfilt/Opts.td
M llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
M llvm/tools/sancov/sancov.cpp
M llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp
M llvm/utils/gn/secondary/compiler-rt/lib/hwasan/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Vectorize/BUILD.gn
M llvm/utils/lit/lit/cl_arguments.py
M llvm/utils/lit/lit/reports.py
A llvm/utils/lit/tests/unique-output-file.py
M mlir/docs/Dialects/Linalg/_index.md
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMiscOps.td
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeDataValues.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
A mlir/test/Conversion/SPIRVToLLVM/barrier-ops-to-llvm.mlir
M mlir/test/Dialect/Linalg/roundtrip.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/lib/Pass/CMakeLists.txt
M mlir/tools/mlir-tblgen/OpDocGen.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/2e596d151ea4...084ae5ad2d09
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