[all-commits] [llvm/llvm-project] 467958: [LLVM][AArch64] Add register classes for Armv9.6 a...

[SpencerAbson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4679583181a9032b4f7c6476c7a1bfefe5724b47
      https://github.com/llvm/llvm-project/commit/4679583181a9032b4f7c6476c7a1bfefe5724b47
  Author: SpencerAbson <Spencer.Abson at arm.com>
  Date:   2024-10-21 (Mon, 21 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
    M llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
    M llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
    M llvm/test/CodeGen/AArch64/fmlal-loreg.ll
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

  Log Message:
  -----------
  [LLVM][AArch64] Add register classes for Armv9.6 assembly (#111717)

Add new register classes/operands and their encoder/decoder behaviour
required for the new Armv9.6 instructions (see
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension).

This work is the basis ofthe 2024 Armv9.6 architecture update effort for
SME.

Co-authored-by: Caroline Concatto caroline.concatto at arm.com
Co-authored-by: Marian Lukac marian.lukac at arm.com
Co-authored-by: Momchil Velikov momchil.velikov at arm.com



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