[all-commits] [llvm/llvm-project] 03dcd8: [RISCV][ISel] Ensure 'in X' Constraints prevent X0...

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 03dcd88c781d06f917750f3a7f6df9ac7f7f67d9
      https://github.com/llvm/llvm-project/commit/03dcd88c781d06f917750f3a7f6df9ac7f7f67d9
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2024-10-18 (Fri, 18 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV][ISel] Ensure 'in X' Constraints prevent X0 (#112563)

I'm not sure if this fix is required, but I've written the patch anyway.
This does not cause test changes, but we haven't got tests that try to
use all 32 registers in inline assembly.

Broadly, for GPRs, we made the explicit choice that `r` constraints
would never attempt to use `x0`, because `x0` isn't really usable like
the other GPRs. I believe the same thing applies to `Zhinx`, `Zfinx` and
`Zdinx` because they should not be allocating operands to `x0` either,
so this patch introduces new `NoX0` classes for `GPRF16` and `GPRF32`
registers, and uses them with inline assembly. There is also a
`GPRPairNoX0` for the `Zdinx` case on rv32, avoiding use of the `x0`
pair which has different behaviour to the other GPR pairs.



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