[all-commits] [llvm/llvm-project] 7f2e93: [SLP]Initial non-power-of-2 support (but still who...

[Alexey Bataev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f2e937469a8cec3fe977bf41ad2dfb9b4ce648a
      https://github.com/llvm/llvm-project/commit/7f2e937469a8cec3fe977bf41ad2dfb9b4ce648a
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2024-10-18 (Fri, 18 Oct 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
    M llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
    M llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
    M llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll

  Log Message:
  -----------
  [SLP]Initial non-power-of-2 support (but still whole register) for reductions

Enables initial non-power-of-2 support (but still requires number of
elements, forming whole registers) for reductions.
Enables extra vectorization for
MultiSource/Benchmarks/7zip/7zip-benchmark, CINT2006/464.h264ref and
CFP2017rate/526.blender_r (checked for SSE2)

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/112361



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