[all-commits] [llvm/llvm-project] fcac60: MachineUniformityAnalysis: Improve isConstantOrUnd...

[Petar Avramovic via All-commits]

  Branch: refs/heads/users/petar-avramovic/new-rbs-phis-with-undef
  Home:   https://github.com/llvm/llvm-project
  Commit: fcac603b2bb731bfd16e415607503c06f3c60d90
      https://github.com/llvm/llvm-project/commit/fcac603b2bb731bfd16e415607503c06f3c60d90
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2024-10-18 (Fri, 18 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineSSAContext.cpp
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/uses-value-from-cycle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-rb-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-rb-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir

  Log Message:
  -----------
  MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi

Change existing code to match what LLVM-IR version is doing via
PHINode::hasConstantOrUndefValue.
Most notably this improves number of values that can be allocated
to sgpr in AMDGPU's RBSelect.
Common case here are phis that appear in structurize-cfg lowering
for cycles with multiple exits:
Undef incoming value is coming from block that reached cycle exit
condition, if other incoming is uniform keep the phi uniform despite
the fact it is joining values from pair of blocks that are entered
via divergent condition branch.



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