[all-commits] [llvm/llvm-project] 5f7502: [AArch64][SVE] Support lowering fixed-length BUILD...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f7502bf1f193482e23385cdd4cfecf09f19ccbc
      https://github.com/llvm/llvm-project/commit/5f7502bf1f193482e23385cdd4cfecf09f19ccbc
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-10-18 (Fri, 18 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll

  Log Message:
  -----------
  [AArch64][SVE] Support lowering fixed-length BUILD_VECTORS to ZIPs (#111698)

This allows lowering fixed-length (non-constant) BUILD_VECTORS (<=
128-bit) to a chain of ZIP1 instructions when Neon is not available,
rather than using the default lowering, which is to spill to the stack
and reload.

For example,

```
t5: v4f32 = BUILD_VECTOR(t0, t1, t2, t3)
```

Becomes:

```
zip1 z0.s, z0.s, z1.s // z0 = t0,t1,...
zip1 z2.s, z2.s, z3.s // z2 = t2,t3,...
zip1 z0.d, z0.d, z2.d // z0 = t0,t1,t2,t3,...
```

When values are already in FRPs, this generally seems to lead to a more
compact output with less movement to/from the stack.



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