[all-commits] [llvm/llvm-project] c5c11f: [lldb-dap] Creating an API for sending dap events ...
Shilei Tian via All-commits
all-commits at lists.llvm.org
Thu Oct 17 06:06:09 PDT 2024
Branch: refs/heads/users/shiltian/autogen-andorbitset
Home: https://github.com/llvm/llvm-project
Commit: c5c11f340436a88cfc2165f2dcd64e4d63285068
https://github.com/llvm/llvm-project/commit/c5c11f340436a88cfc2165f2dcd64e4d63285068
Author: John Harrison <harjohn at google.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
A lldb/test/API/tools/lldb-dap/send-event/Makefile
A lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
A lldb/test/API/tools/lldb-dap/send-event/main.c
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/README.md
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Creating an API for sending dap events from a script in lldb-dap. (#112384)
Custom DAP events can be detected using
https://code.visualstudio.com/api/references/vscode-api#debug.onDidReceiveDebugSessionCustomEvent.
This API allows an lldb python script to send events to the DAP
client to allow extensions to handle these custom events.
Commit: 90767bc41bd69fb4b9ac01a8420ef58bbbaeab7c
https://github.com/llvm/llvm-project/commit/90767bc41bd69fb4b9ac01a8420ef58bbbaeab7c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/debugserver/source/libdebugserver.cpp
Log Message:
-----------
[lldb] Remove more mentions of ASLLogCallback (#112639)
Commit: f5aee1f18bdbc5694330a5e86eb46cf60e653d0c
https://github.com/llvm/llvm-project/commit/f5aee1f18bdbc5694330a5e86eb46cf60e653d0c
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/EmulateNarrowType.cpp
M mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
M mlir/lib/Dialect/MemRef/Transforms/EmulateWideInt.cpp
M mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
M mlir/test/Dialect/MemRef/emulate-wide-int.mlir
Log Message:
-----------
[mlir][memref] Fix type conversion in emulate-wide-int and emulate-narrow-type (#112214)
This PR follows with #112104, using `nullptr` to indicate that type
conversion failed and no fallback conversion should be attempted.
Commit: 9930a5a3338ba642c52292107e0f729328d79034
https://github.com/llvm/llvm-project/commit/9930a5a3338ba642c52292107e0f729328d79034
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
Log Message:
-----------
[mlir][tosa] Update document of `tosa.rescale`(NFC) (#112531)
This PR formats the `supported rescalings` using a table. The previous
structure was disorganized, as seen in the documentation:
https://mlir.llvm.org/docs/Dialects/TOSA/#tosarescale-mlirtosarescaleop.
Commit: 4c98a71993ddba09ab6e81c905d2a1cc08d8d76e
https://github.com/llvm/llvm-project/commit/4c98a71993ddba09ab6e81c905d2a1cc08d8d76e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/tests/sanitizer_posix_test.cpp
Log Message:
-----------
[nfc][sanitizer] Unmap memory in test (#112644)
Commit: dd9a34fd7e6cb190d44d310a610e9f959e2e599f
https://github.com/llvm/llvm-project/commit/dd9a34fd7e6cb190d44d310a610e9f959e2e599f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M compiler-rt/lib/lsan/lsan_common.cpp
Log Message:
-----------
[nfc][lsan] Move up vectors cleanup (#112608)
Commit: 6ffd3bbcd7240f2a23cec99c11b7298cc28f54c5
https://github.com/llvm/llvm-project/commit/6ffd3bbcd7240f2a23cec99c11b7298cc28f54c5
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M compiler-rt/lib/lsan/lsan_common.cpp
Log Message:
-----------
[nfc][lsan] Restructure loop in ProcessThreads (#112609)
The goal is to move `SuspendedThreadsList` related code into
the beginning of the loop, and prepare for extraction the rest
of the loop body into a function.
Commit: 5e9166e02ab65d42efba014f2adc59c42b097ddc
https://github.com/llvm/llvm-project/commit/5e9166e02ab65d42efba014f2adc59c42b097ddc
Author: Jim Lin <jim at andestech.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Remove TTI parameter from vectorizeHorReduction and vectorizeRootInstruction. NFC.
Since TTI is a member variable.
Commit: d54953ef472bfd8d4b503aae7682aa76c49f8cc0
https://github.com/llvm/llvm-project/commit/d54953ef472bfd8d4b503aae7682aa76c49f8cc0
Author: Wu Yingcong <yingcong.wu at intel.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerExtFunctionsWindows.cpp
Log Message:
-----------
[fuzzer] fix clang-cl build fuzzer lit test failure (#112339)
The `check-fuzzer` runs fine with cl build llvm, but the following lit
tests fail with clang-cl build llvm
```
********************
Timed Out Tests (2):
libFuzzer-x86_64-default-Windows :: fork-ubsan.test
libFuzzer-x86_64-default-Windows :: fuzzer-oom.test
********************
Failed Tests (22):
libFuzzer-x86_64-default-Windows :: acquire-crash-state.test
libFuzzer-x86_64-default-Windows :: cross_over_copy.test
libFuzzer-x86_64-default-Windows :: cross_over_insert.test
libFuzzer-x86_64-default-Windows :: exit_on_src_pos.test
libFuzzer-x86_64-default-Windows :: fuzzer-alignment-assumption.test
libFuzzer-x86_64-default-Windows :: fuzzer-implicit-integer-sign-change.test
libFuzzer-x86_64-default-Windows :: fuzzer-implicit-signed-integer-truncation-or-sign-change.test
libFuzzer-x86_64-default-Windows :: fuzzer-implicit-signed-integer-truncation.test
libFuzzer-x86_64-default-Windows :: fuzzer-implicit-unsigned-integer-truncation.test
libFuzzer-x86_64-default-Windows :: fuzzer-printcovpcs.test
libFuzzer-x86_64-default-Windows :: fuzzer-timeout.test
libFuzzer-x86_64-default-Windows :: fuzzer-ubsan.test
libFuzzer-x86_64-default-Windows :: minimize_crash.test
libFuzzer-x86_64-default-Windows :: minimize_two_crashes.test
libFuzzer-x86_64-default-Windows :: null-deref-on-empty.test
libFuzzer-x86_64-default-Windows :: null-deref.test
libFuzzer-x86_64-default-Windows :: print-func.test
libFuzzer-x86_64-default-Windows :: stack-overflow-with-asan.test
libFuzzer-x86_64-default-Windows :: trace-malloc-2.test
libFuzzer-x86_64-default-Windows :: trace-malloc-unbalanced.test
libFuzzer-x86_64-default-Windows :: trace-malloc.test
```
The related commits are
https://github.com/llvm/llvm-project/commit/53a81d4d26f0409de8a0655d7af90f2bea222a12
and
https://github.com/llvm/llvm-project/commit/e31efd8f6fbc27000a4933f889e0deb922411006.
Following the change in
https://github.com/llvm/llvm-project/commit/e31efd8f6fbc27000a4933f889e0deb922411006
can fix these failures.
As for the issue mentioned in the comment that alternatename support in
clang not good enough(https://bugs.llvm.org/show_bug.cgi?id=40218). I
find that using `__builtin_function_start(func)` instead of directly
using `func` would make it work as intended.
Commit: 1b4a173fa41e02eddec9f1cf41324aa4ea8a7fa5
https://github.com/llvm/llvm-project/commit/1b4a173fa41e02eddec9f1cf41324aa4ea8a7fa5
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Remove unneeded LoopScalarBody member variable. (NFC)
Commit: 4512bbe7467c1c0f884304e5654d1070df58d6f8
https://github.com/llvm/llvm-project/commit/4512bbe7467c1c0f884304e5654d1070df58d6f8
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
Log Message:
-----------
[HLSL] Collect explicit resource binding information (#111203)
Scans each global variable declaration and its members and collects all
required resource bindings in a new `SemaHLSL` data member `Bindings`.
New fields are added `HLSLResourceBindingAttr` for storing processed
binding information so that it can be used by CodeGen (`Bindings` or any
other Sema information is not accessible from CodeGen.)
Adjusts the existing register binding attribute handling and diagnostics
to:
- do not create HLSLResourceBindingAttribute if it is not valid
- diagnose only the simple/local errors when a register binding
attribute is parsed
- additional diagnostic of binding type mismatches is done later and
uses the new `Bindings` data
Fixes #110719
Commit: 81bbe19383797d5daaa5ddd16a47cd6ff44b66e2
https://github.com/llvm/llvm-project/commit/81bbe19383797d5daaa5ddd16a47cd6ff44b66e2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Add VPSingleDefRecipe::dump() to resolve ambigous lookup (NFC).
This allows calling ::dump() on various sub-classes of VPSingleDefRecipe
directly, as it resolves an ambigous name lookup.
Previously, calling VPWidenRecipe::dump() (and others), would result in
the following errors:
llvm/unittests/Transforms/Vectorize/VPlanTest.cpp:1284:19: error: member 'dump' found in multiple base classes of different types
1284 | WidenR->dump();
| ^
llvm/include/../lib/Transforms/Vectorize/VPlanValue.h:434:8: note: member found by ambiguous name lookup
434 | void dump() const;
| ^
llvm/include/../lib/Transforms/Vectorize/VPlanValue.h:108:8: note: member found by ambiguous name lookup
108 | void dump() const;
| ^
1 error generated.
Commit: 927af63fddb8e34f23b2974f812156767988ec5f
https://github.com/llvm/llvm-project/commit/927af63fddb8e34f23b2974f812156767988ec5f
Author: thetruestblue <92476612+thetruestblue at users.noreply.github.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
A clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
M llvm/include/llvm/Transforms/Utils/Instrumentation.h
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
Log Message:
-----------
[SanitizerCoverage] Add an option to gate the invocation of the tracing callbacks (#108328)
Implement -sanitizer-coverage-gated-trace-callbacks to gate the
invocation of the tracing callbacks based on the value of a global
variable, which is stored in a specific section.
When this option is enabled, the instrumentation will not call into the
runtime-provided callbacks for tracing, thus only incurring in a trivial
branch without going through a function call. It is up to the runtime to
toggle the value of the global variable in order to enable tracing.
This option is only supported for trace-pc-guard.
Note: will add additional support for trace-cmp in a follow up PR.
Patch by Filippo Bigarella
rdar://101626834
Commit: 3142dff70401086a14ee9ae3428f65f5dfa6a2e6
https://github.com/llvm/llvm-project/commit/3142dff70401086a14ee9ae3428f65f5dfa6a2e6
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-10-16 (Wed, 16 Oct 2024)
Changed paths:
M compiler-rt/lib/lsan/lsan_common.cpp
Log Message:
-----------
[nfc][lsan] Extract significant part of the loop into a function (#112610)
Co-authored-by: thetruestblue <92476612+thetruestblue at users.noreply.github.com>
Commit: 23d4fe6c5c52e054bbed75e78104f59869337356
https://github.com/llvm/llvm-project/commit/23d4fe6c5c52e054bbed75e78104f59869337356
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV] Fix gcc -Wparentheses warning [NFC]
Without this gcc warned like
../lib/Target/RISCV/RISCVVLOptimizer.cpp:760: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
760 | VLOp.getReg() != RISCV::X0 && "Did not expect X0 VL");
|
Commit: 3ae6b57671744b4fe4dd76769cce0745a0f5bc31
https://github.com/llvm/llvm-project/commit/3ae6b57671744b4fe4dd76769cce0745a0f5bc31
Author: Lang Hames <lhames at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
Log Message:
-----------
[ORC] Remove extraneous lines in comment.
Commit: 255a99c29f9fa1a89b03a85a3a73d6f44d03c6c1
https://github.com/llvm/llvm-project/commit/255a99c29f9fa1a89b03a85a3a73d6f44d03c6c1
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/CodeGen/CGVTT.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/Parse/ParseInit.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M lldb/source/Expression/DWARFExpression.cpp
M llvm/include/llvm/ADT/APFixedPoint.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/ExecutionEngine/MCJIT/MCJIT.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/unittests/ADT/APFixedPointTest.cpp
Log Message:
-----------
[APInt] Fix APInt constructions where value does not fit bitwidth (NFCI) (#80309)
This fixes all the places that hit the new assertion added in
https://github.com/llvm/llvm-project/pull/106524 in tests. That is,
cases where the value passed to the APInt constructor is not an N-bit
signed/unsigned integer, where N is the bit width and signedness is
determined by the isSigned flag.
The fixes either set the correct value for isSigned, set the
implicitTrunc flag, or perform more calculations inside APInt.
Note that the assertion is currently still disabled by default, so this
patch is mostly NFC.
Commit: 267be4a7f4ac69cfd1bec5223554bbe400c5636c
https://github.com/llvm/llvm-project/commit/267be4a7f4ac69cfd1bec5223554bbe400c5636c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/lib/IR/Builders.cpp
Log Message:
-----------
[MLIR] Reference issue for implicit trunc TODOs (NFC)
Commit: 1cc5290a30a0d6dffeb2e0f475558fcf3ded8e1f
https://github.com/llvm/llvm-project/commit/1cc5290a30a0d6dffeb2e0f475558fcf3ded8e1f
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
Log Message:
-----------
[AMDGPU] Factor out getNumUsedPhysRegs(). NFC. (#112624)
I will need it from one more place.
Commit: cb9bacf57d5c58eba28a76fd07ea2d4f9a0da847
https://github.com/llvm/llvm-project/commit/cb9bacf57d5c58eba28a76fd07ea2d4f9a0da847
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M bolt/lib/Passes/LongJmp.cpp
A bolt/test/AArch64/split-funcs-lite.s
Log Message:
-----------
[AArch64][BOLT] Ensure tentative code layout for cold BBs runs. (#96609)
When split functions is used, BOLT may skip tentative code layout
estimation in some cases, like:
- when there is no profile data for some blocks (ie cold blocks)
- when there are cold functions in lite mode
- when skip functions is used
However, when rewriting the binary we still need to compute PC-relative
distances between hot and cold basic blocks. Without cold layout
estimation, BOLT uses '0x0' as the address of the first cold block,
leading to incorrect estimations of any PC-relative addresses.
This affects large binaries as the relaxStub method expands more
branches than necessary using the short-jump sequence, at it wrongly
believes it has exceeded the branch distance boundary.
This increases code size with both a larger and slower sequence;
however,
performance regression is expected to be minimal since this only affects
any called cold code.
Example of such an unnecessary relaxation:
from:
```armasm
b .Ltmp1234
```
to:
```armasm
adrp x16, .Ltmp1234
add x16, x16, :lo12:.Ltmp1234
br x16
```
Commit: 9d5ceccbd909398babd1ab71d62b0b708bb066c0
https://github.com/llvm/llvm-project/commit/9d5ceccbd909398babd1ab71d62b0b708bb066c0
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M compiler-rt/test/ubsan/TestCases/Misc/Posix/ubsan_options.cpp
Log Message:
-----------
Speculatively un-XFAIL TestCases/Misc/Posix/ubsan_options.cpp on Darwin
After https://github.com/llvm/llvm-project/pull/111497 the test started
unexpectedly passing (https://crbug.com/373891811), probably because it
does actually work but wasn't run when it lived in the Misc/Linux/
directory.
Commit: 4cda28c1ada702a08f6960eb4c93919187c1d4d1
https://github.com/llvm/llvm-project/commit/4cda28c1ada702a08f6960eb4c93919187c1d4d1
Author: Byoungchan Lee <byoungchan.lee at gmx.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang-tools-extra/include-cleaner/test/tool.cpp
M clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp
Log Message:
-----------
[clang-include-cleaner] Fix incorrect directory issue for writing files (#111375)
If the current working directory of `clang-include-cleaner` differs from
the directory of the input files specified in the compilation database,
it doesn't adjust the input file paths properly. As a result,
`clang-include-cleaner` either writes files to the wrong directory or
fails to write files altogether.
This pull request fixes the issue by adjusting the input file paths
based on the directory specified in the compilation database. If that
directory is not writable, `clang-include-cleaner` will write the output
relative to the current working directory.
Fixes #110843.
Commit: cb43021e5726a4462f28a999fb66a8dc20dc354b
https://github.com/llvm/llvm-project/commit/cb43021e5726a4462f28a999fb66a8dc20dc354b
Author: CarolineConcatto <caroline.concatto at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/include/clang/Basic/AArch64SVEACLETypes.def
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/Type.cpp
M clang/test/AST/ast-dump-aarch64-sve-types.c
M clang/test/CodeGen/aarch64-sve.c
M clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
M clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
M clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp
M clang/test/CodeGenObjC/aarch64-sve-types.m
M clang/test/Modules/no-external-type-id.cppm
M clang/test/Sema/aarch64-sve-types.c
A clang/test/Sema/arm-mfp8.cpp
M clang/test/SemaObjC/aarch64-sve-types.m
M clang/utils/TableGen/SveEmitter.cpp
Log Message:
-----------
[CLANG]Add Scalable vectors for mfloat8_t (#101644)
This patch adds these new vector sizes for sve:
svmfloat8_t
According to the ARM ACLE PR#323[1].
[1] ARM-software/acle#323
Commit: e1f8f84acec05997893c305c78fbf7feecf44dd7
https://github.com/llvm/llvm-project/commit/e1f8f84acec05997893c305c78fbf7feecf44dd7
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
A llvm/test/CodeGen/Thumb2/pacbti-m-frame-chain.ll
Log Message:
-----------
[ARM] Fix frame chains with M-profile PACBTI (#110285)
When using AAPCS-compliant frame chains with PACBTI return address
signing, there ware a number of bugs in the generation of the frame
pointer and function prologues. The most obvious was that we sometimes
would modify r11 before pushing it to the stack, so it wasn't preserved
as required by the PCS. We also sometimes did not push R11 and LR
adjacent to one another on the stack, or used R11 as a frame pointer
without pointing it at the saved value of R11, both of which are
required to have an AAPCS compliant frame chain.
The original work of this patch was done by James Westwood, reviewed as
#82801 and #81249, with some tidy-ups done by Mark Murray and myself.
Commit: 671976ff59ac893c2e97a95860510afa5d5e9a84
https://github.com/llvm/llvm-project/commit/671976ff59ac893c2e97a95860510afa5d5e9a84
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/simple_early_exit.ll
Log Message:
-----------
[NFC][LoopVectorize] Add more simple early exit tests (#112529)
I realised we are missing tests to cover more loops with multiple early
exits - some countable and some uncountable.
I've also added a few SVE versions of the test in the AArch64 directory.
Once we can vectorise such early exit loops it's a good sanity check to
make sure they also vectorise for SVE. Also, for some of the tests I
expect there to be some divergence from the same tests in the top level
directory once we start vectorising them.
Commit: d51af6c215fce3d6d3791dbfdb3d0c6296dd0bf9
https://github.com/llvm/llvm-project/commit/d51af6c215fce3d6d3791dbfdb3d0c6296dd0bf9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/prefer-avx256-mulo.ll
M llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
Log Message:
-----------
[X86] Regenerate test checks with vpternlog comments
Commit: 375690c0a1a1caacad1bbd243a611ae5c2970996
https://github.com/llvm/llvm-project/commit/375690c0a1a1caacad1bbd243a611ae5c2970996
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/test/Driver/hip-include-path.hip
Log Message:
-----------
clang/HIP: Remove REQUIRES libgcc from a test (#112412)
Commit: 77ea619bc6cdcdf734105e0c96c92e060aadc011
https://github.com/llvm/llvm-project/commit/77ea619bc6cdcdf734105e0c96c92e060aadc011
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/test/Driver/hip-runtime-libs-msvc.hip
Log Message:
-----------
clang/HIP: Remove REQUIRES windows from a test (#112411)
Commit: 6902b39b6ffda5ad1253147740fb04befbf82333
https://github.com/llvm/llvm-project/commit/6902b39b6ffda5ad1253147740fb04befbf82333
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
M mlir/lib/Dialect/Arith/Transforms/UnsignedWhenEquivalent.cpp
M mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir
Log Message:
-----------
[mlir] UnsignedWhenEquivalent: use greedy rewriter instead of dialect conversion (#112454)
`UnsignedWhenEquivalent` doesn't really need any dialect conversion
features and switching it normal patterns makes it more composable with
other patterns-based transformations (and probably faster).
Commit: 9b713f5d234adec266d46c9cfc3f2607793976dc
https://github.com/llvm/llvm-project/commit/9b713f5d234adec266d46c9cfc3f2607793976dc
Author: Pradeep Kumar <pradeepku at nvidia.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][NVVM] Add PTX predefined special registers (#112343)
This commit adds support for the following PTX predefined special
registers
* warpid
* nwarpid
* smid
* nsmid
* gridid
* lanemask.*
* globaltimer
* envreg* And added lit tests under nvvmir.mlir
Commit: 2ab2539ce95bd3330370e703020a28eca89ea872
https://github.com/llvm/llvm-project/commit/2ab2539ce95bd3330370e703020a28eca89ea872
Author: Youngsuk Kim <joseph942010 at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
Log Message:
-----------
[polly] Avoid llvm::Type::getPointerTo() (NFC) (#112651)
`llvm::Type::getPointerTo()` is to be deprecated & removed soon.
Commit: b584478e0068fd627b7f5e9f63574caab78cc56e
https://github.com/llvm/llvm-project/commit/b584478e0068fd627b7f5e9f63574caab78cc56e
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/test/Driver/aarch64-v96a.c
M clang/test/Driver/print-supported-extensions-aarch64.c
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Introduce new armv9.6 features (#111677)
This patch implements new features introduced in 2024 release of ARM ISA
and creates predicates, which will be used by new instructions.
Co-authored-by: Caroline Concatto caroline.concatto at arm.com
Co-authored-by: Spencer Abson spencer.abson at arm.com
Commit: 4091bc61e315f187829dca877dd908a07ba9cb91
https://github.com/llvm/llvm-project/commit/4091bc61e315f187829dca877dd908a07ba9cb91
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
Log Message:
-----------
[MLIR][OpenMP] Split region-associated op verification (#112355)
This patch moves the part of operation verifiers dependent on the
contents of their regions to the corresponding `verifyRegions` method.
This ensures these are only triggered after the operations in the region
have themselved already been verified in advance, avoiding checks based
on invalid nested operations.
The `LoopWrapperInterface` is also updated so that its verifier runs
after operations in the region of ops with this interface have already
been verified.
Commit: b091701d0190912578ac3fe91ee8fd29e9b6de6e
https://github.com/llvm/llvm-project/commit/b091701d0190912578ac3fe91ee8fd29e9b6de6e
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/include/mlir/IR/MLIRContext.h
M mlir/lib/IR/MLIRContext.cpp
Log Message:
-----------
[mlir] Add a method on MLIRContext to retrieve the operations for a given dialect (#112344)
Currently we have `MLIRContext::getRegisteredOperations` which returns
all operations for the given context, with the addition of
`MLIRContext::getRegisteredOperationsByDialect` we can now retrieve the
same for a given dialect class.
Closes #111591
Commit: ad45eb4a9c74a878998efe8fd734f5ae7af5003d
https://github.com/llvm/llvm-project/commit/ad45eb4a9c74a878998efe8fd734f5ae7af5003d
Author: John Brawn <john.brawn at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/test/MC/ARM/vlstm-vlldm-diag.s
M llvm/test/MC/ARM/vscclrm-asm.s
M llvm/test/MC/Disassembler/ARM/vscclrm.txt
Log Message:
-----------
[ARM] Fix problems with register list in vscclrm (#111825)
The register list in vscclrm is unusual in three ways:
* The encoded size can be zero, meaning the list contains only vpr.
* Double-precision registers past d15 are permitted even when the
subtarget doesn't have them, they are instead ignored when the
instruction executes.
* The single-precision variant allows double-precision registers d16
onwards, which are encoded as a pair of single-precision registers.
Fixing this also incidentally changes a vlldm/vlstm error message: when
the first register is in the range d16-d31 we now get the "operand must
be exactly..." error instead of "register expected".
Commit: 53d89ef34005f4dc4f764db0c009130bb52a6a78
https://github.com/llvm/llvm-project/commit/53d89ef34005f4dc4f764db0c009130bb52a6a78
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/test/Sema/aarch64-neon-target.c
A clang/test/Sema/aarch64-vcmla-undef.c
Log Message:
-----------
[AArch64][Clang][NEON] Remove undefined vcmla intrinsics (#112575)
arm_neon.td currently generates the same 24 `vcmla` intrinsic prototypes
for each of the f16, f32, and f64 base types. This is incorrect, the
only valid vcmla intrinsics for the f64 base type are:
- `vcmlaq_f64`
- `vcmlaq_rot90_f64`
- `vcmlaq_rot180_f64`
- `vcmlaq_rot270_f64`
(see ACLE
https://github.com/ARM-software/acle/blob/main/neon_intrinsics/advsimd.md)
This patch removes the incorrect intrinsic prototypes.
Commit: 5b4071c7554ab4feeae4817e3d41013016308586
https://github.com/llvm/llvm-project/commit/5b4071c7554ab4feeae4817e3d41013016308586
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
Log Message:
-----------
[clang][bytecode] Explicitly truncate in IntegralAP::from() (#112683)
Add Integral::toAPInt(), which truncates to the given BitWidth, similar
to the toAPSInt() we already have.
Commit: 125168744810fffff4aba039208afd9ffe1d11b1
https://github.com/llvm/llvm-project/commit/125168744810fffff4aba039208afd9ffe1d11b1
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove a leftover dump call
Commit: 4d228e1ebdd652ad3c95e64c0f1bae17145e9e1b
https://github.com/llvm/llvm-project/commit/4d228e1ebdd652ad3c95e64c0f1bae17145e9e1b
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/test/Conversion/VectorToLLVM/vector-xfer-to-llvm.mlir
Log Message:
-----------
[mlir][vector] Escape variable usage in test
Otherwise the shell might expand this in the command line.
Commit: 584e00a3161ca51ef9b47acb37a653aa881de0a6
https://github.com/llvm/llvm-project/commit/584e00a3161ca51ef9b47acb37a653aa881de0a6
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
Log Message:
-----------
[ARM] Fix -Wunused-variable in ARMFrameLowering.cpp (NFC)
/llvm-project/llvm/lib/Target/ARM/ARMFrameLowering.cpp:1028:9:
error: unused variable 'FPOffset' [-Werror,-Wunused-variable]
int FPOffset = MFI.getObjectOffset(FramePtrSpillFI);
^
1 error generated.
Commit: 2954d1f7bc8fa77c51768855d9df98f5559a5c5e
https://github.com/llvm/llvm-project/commit/2954d1f7bc8fa77c51768855d9df98f5559a5c5e
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp
Log Message:
-----------
[include-cleaner] Fix -Wpessimizing-move in IncludeCleaner.cpp (NFC)
/llvm-project/clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp:302:14:
error: moving a temporary object prevents copy elision [-Werror,-Wpessimizing-move]
return std::move(llvm::errorCodeToError(Err));
^
/llvm-project/clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp:302:14: note: remove std::move call here
return std::move(llvm::errorCodeToError(Err));
^~~~~~~~~~ ~
1 error generated.
Commit: ab90d2793cf56758a91f7a7ae027850af2455d3e
https://github.com/llvm/llvm-project/commit/ab90d2793cf56758a91f7a7ae027850af2455d3e
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-dest-non-array.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-global-dest.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-non-byte-array.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-non-const-global.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-string-multi-use.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-1.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-2.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-lengths-dont-match.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-more-than-64-bytes.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-ptrtoint.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-struct-test.ll
A llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-volatile.ll
Log Message:
-----------
[llvm][ARM]Add widen global arrays pass (#107120)
- Pass optimizes memcpy's by padding out destinations and sources to a
full word to make backend generate full word loads instead of loading a
single byte (ldrb) and/or half word (ldrh). Only pads destination when
it's a stack allocated constant size array and source when it's constant
array. Heuristic to decide whether to pad or not is very basic and could
be improved to allow more examples to be padded.
- Pass works within GlobalOpt but is disabled by default on all targets
except ARM.
Commit: 83953c7df107af26ebf9ab82e01623c991637199
https://github.com/llvm/llvm-project/commit/83953c7df107af26ebf9ab82e01623c991637199
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Support/APInt.cpp
Log Message:
-----------
APInt.cpp: Prune a stray semicolon.
Commit: 5bcc66dc009893c55aefdcd16a0ca2dad315481b
https://github.com/llvm/llvm-project/commit/5bcc66dc009893c55aefdcd16a0ca2dad315481b
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/lib/CodeGen/CoverageMappingGen.cpp
Log Message:
-----------
VisitIfStmt: Prune a redundant condition.
`S->isConsteval()` is evaluated at the top of this method.
Likely mis-merging in #75425
Commit: 40d9561b2d5651e3d2ffa057d2b89cb8d5146fb9
https://github.com/llvm/llvm-project/commit/40d9561b2d5651e3d2ffa057d2b89cb8d5146fb9
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingMerge.c
Log Message:
-----------
InstrProfilingMerge.c: Fix potential misalignment in `SrcBitmapStart`
Currently it is not an issue. It will be a problem if Bitmap is
located after single byte counters.
Commit: 9c80eb7c83c6471d4126ef46f85bf673787de521
https://github.com/llvm/llvm-project/commit/9c80eb7c83c6471d4126ef46f85bf673787de521
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
Silence -Wswitch after cb43021e5726a4462f28a999fb66a8dc20dc354b
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp:4885:13: warning: enumeration value 'SveMFloat8' not handled in switch [-Wswitch]
4885 | switch (llvm::cast<clang::BuiltinType>(qual_type)->getKind()) {
|
Commit: 2f0b4f43fc5c1e7587c4d00daa9cc230df2f8a2d
https://github.com/llvm/llvm-project/commit/2f0b4f43fc5c1e7587c4d00daa9cc230df2f8a2d
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/optional.fir
Log Message:
-----------
[flang][extension] support concatenation with absent optional (#112678)
Fix #112593 by adding support in lowering to concatenation with an
absent optional _assumed length_ dummy argument because:
1. Most compilers seem to support it (most likely by accident).
2. This actually makes the compiler codegen simpler. Codegen was going
out of its way to poke the LLVM optimizer bear by producing an undef
argument for the length.
I insist on the fact that no compiler support this with _explicit
length_ optional arguments and the executable will segfault and I would
discourage users from using that "feature" because runtime checks for
bad optional dereference will kick when used (For instance, "nagfor
-C=present" will produce an executable that abort with an error message
. Flang does not have such runtime check option so far).
Hence, I am not updating the Extensions.md document because this is not
something I think we should advertise.
Commit: e21c80ac73a9da5c86c20dbce37c9227a17ab06a
https://github.com/llvm/llvm-project/commit/e21c80ac73a9da5c86c20dbce37c9227a17ab06a
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/lib/Parse/ParseStmt.cpp
M clang/test/Sema/constexpr.c
Log Message:
-----------
[clang] Reject if constexpr in C (#112685)
Fixes https://github.com/llvm/llvm-project/issues/112587
Commit: 2882bb192b07674bc11fd5ddd5a4fa6cea194628
https://github.com/llvm/llvm-project/commit/2882bb192b07674bc11fd5ddd5a4fa6cea194628
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M lldb/docs/index.rst
Log Message:
-----------
[lldb][docs] Add link to LoongArch tracking issue
https://github.com/llvm/llvm-project/issues/112693 will be
tracking the overall state of LoongArch support.
This means anyone can check without having to track down
an expert.
Commit: f42785d0c8886a65fbdd160b0ef47baa5931e582
https://github.com/llvm/llvm-project/commit/f42785d0c8886a65fbdd160b0ef47baa5931e582
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
Log Message:
-----------
[Polly] Remove unused variable 'IdentTy' in LoopGeneratorsKMP.cpp (NFC)
/llvm-project/polly/lib/CodeGen/LoopGeneratorsKMP.cpp:396:15: error: unused variable 'IdentTy' [-Werror,-Wunused-variable]
StructType *IdentTy =
^
/llvm-project/polly/lib/CodeGen/LoopGeneratorsKMP.cpp:460:15: error: unused variable 'IdentTy' [-Werror,-Wunused-variable]
StructType *IdentTy =
^
2 errors generated.
Commit: 067e8b8dc54b2558548c248ae851a0e01cb05878
https://github.com/llvm/llvm-project/commit/067e8b8dc54b2558548c248ae851a0e01cb05878
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
DAG: Lower fcNormal is.fpclass to compare with inf (#100389)
Commit: 8268bc48eb32b006700f6f6b7da0971a2336ab42
https://github.com/llvm/llvm-project/commit/8268bc48eb32b006700f6f6b7da0971a2336ab42
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] Avoid SDLoc duplication in FP<->INT combines. NFC.
Commit: 784c15a282803b23b451b51c533eb5df93fda874
https://github.com/llvm/llvm-project/commit/784c15a282803b23b451b51c533eb5df93fda874
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] visitSINT_TO_FP/UINT_TO_FP - use FoldConstantArithmetic to attempt to constant fold
Don't rely on isConstantIntBuildVectorOrConstantInt followed by getNode() will constant fold - FoldConstantArithmetic will do all of this for us.
Cleanup for #112682
Commit: 5692a0c6f846f9b1bacd445f4adedadf66c558ea
https://github.com/llvm/llvm-project/commit/5692a0c6f846f9b1bacd445f4adedadf66c558ea
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] visitFP_TO_SINT/FP_TO_UINT - use FoldConstantArithmetic to attempt to constant fold
Don't rely on isConstantFPBuildVectorOrConstantFP followed by getNode() will constant fold - FoldConstantArithmetic will do all of this for us.
Cleanup for #112682
Commit: bf5cf82dd471a7c561d0f0a60ff4c8eaa1d20ff9
https://github.com/llvm/llvm-project/commit/bf5cf82dd471a7c561d0f0a60ff4c8eaa1d20ff9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Log Message:
-----------
Fix MSVC signed/unsigned mismatch warning. NFC.
Commit: cf046c8717468d4a4ff8d8080dcb1ba316edbea9
https://github.com/llvm/llvm-project/commit/cf046c8717468d4a4ff8d8080dcb1ba316edbea9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] visitSIGN_EXTEND_INREG - avoid SDLoc duplication. NFC.
Commit: c980a20b105c9298a5975b6944417f17cf772b6b
https://github.com/llvm/llvm-project/commit/c980a20b105c9298a5975b6944417f17cf772b6b
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
Log Message:
-----------
[AArch64][SVE] Enable max vector bandwidth for SVE (#109671)
Returns true for shouldMaximizeVectorBandwidth when the register type
is a scalable vector and SVE or streaming SVE are available.
Commit: 4a2bd78f5b0d0661c23dff9c4b93a393a49dbf9a
https://github.com/llvm/llvm-project/commit/4a2bd78f5b0d0661c23dff9c4b93a393a49dbf9a
Author: gxlayer <151722229+guoxin049 at users.noreply.github.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/TargetOptionsImpl.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.h
M llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
M llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/ARM/atomic-load-store.ll
M llvm/test/CodeGen/ARM/call-tc.ll
M llvm/test/CodeGen/ARM/debug-frame.ll
M llvm/test/CodeGen/ARM/ehabi.ll
M llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
M llvm/test/CodeGen/ARM/frame-chain.ll
M llvm/test/CodeGen/ARM/ifcvt5.ll
M llvm/test/CodeGen/ARM/ldrd.ll
M llvm/test/CodeGen/ARM/stack-frame-layout-remarks.ll
M llvm/test/CodeGen/ARM/stack-size-section.ll
M llvm/test/CodeGen/ARM/swifterror.ll
M llvm/test/CodeGen/ARM/v7k-abi-align.ll
M llvm/test/CodeGen/Thumb/frame-chain.ll
M llvm/test/CodeGen/Thumb2/frame-pointer.ll
M llvm/test/CodeGen/Thumb2/frameless.ll
M llvm/test/CodeGen/Thumb2/frameless2.ll
M llvm/test/CodeGen/Thumb2/machine-licm.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected
Log Message:
-----------
[ARM] Fix -mno-omit-leaf-frame-pointer flag doesn't works on 32-bit ARM (#109628)
The -mno-omit-leaf-frame-pointer flag works on 32-bit ARM architectures
and addresses the bug reported in #108019
Commit: 0f7d148db45e782373c5d6a0faf745986753982b
https://github.com/llvm/llvm-project/commit/0f7d148db45e782373c5d6a0faf745986753982b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Log Message:
-----------
[InstCombine] Add shared helper for logical and bitwise and/or (NFC)
Add a helper for shared folds between logical and bitwise and/or
and move the and/or of icmp and fcmp folds in there. This makes
it easier to extend to more folds.
A possible extension would be to base the current and/or of icmp
reassociation logic on this helper, so that it for example also
applies to fcmp.
Commit: 370fd74361be476ff17ecf8fa3c36ae9f51b9e0e
https://github.com/llvm/llvm-project/commit/370fd74361be476ff17ecf8fa3c36ae9f51b9e0e
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-dest-non-array.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-global-dest.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-non-byte-array.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-non-const-global.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-string-multi-use.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-1.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-2.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-lengths-dont-match.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-more-than-64-bytes.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-ptrtoint.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-struct-test.ll
R llvm/test/Transforms/GlobalOpt/ARM/arm-widen-strings-volatile.ll
Log Message:
-----------
Revert "[llvm][ARM]Add widen global arrays pass" (#112701)
Reverts llvm/llvm-project#107120
Unexpected build failures in post-commit pipelines. Needs investigation
Commit: 095d49da76be09143582e07a807c86d3b4334dec
https://github.com/llvm/llvm-project/commit/095d49da76be09143582e07a807c86d3b4334dec
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Analysis/ValueTracking/non-negative-phi-bits.ll
M llvm/test/Transforms/InstCombine/call-guard.ll
M llvm/test/Transforms/InstCombine/cast_phi.ll
M llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
M llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll
M llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll
M llvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/icmp-mul.ll
M llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
M llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll
M llvm/test/Transforms/InstCombine/icmp-range.ll
M llvm/test/Transforms/InstCombine/icmp-shr.ll
M llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-vscale.ll
M llvm/test/Transforms/InstCombine/icmp.ll
M llvm/test/Transforms/InstCombine/icmp_sdiv_with_and_without_range.ll
M llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
M llvm/test/Transforms/InstCombine/ispow2.ll
M llvm/test/Transforms/InstCombine/load-bitcast-select.ll
M llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/memchr.ll
M llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll
M llvm/test/Transforms/InstCombine/pr100298.ll
M llvm/test/Transforms/InstCombine/pr63791.ll
M llvm/test/Transforms/InstCombine/rem.ll
M llvm/test/Transforms/InstCombine/remove-loop-phi-multiply-by-zero.ll
M llvm/test/Transforms/InstCombine/strchr-1.ll
M llvm/test/Transforms/InstCombine/sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
M llvm/test/Transforms/PhaseOrdering/X86/ctlz-loop.ll
M llvm/test/Transforms/PhaseOrdering/gvn-replacement-vs-hoist.ll
Log Message:
-----------
[InstCombine] Set `samesign` when converting signed predicates into unsigned (#112642)
Alive2: https://alive2.llvm.org/ce/z/6cqdt-
Commit: 388d7f144880dcd85ff31f06793304405a9f44b6
https://github.com/llvm/llvm-project/commit/388d7f144880dcd85ff31f06793304405a9f44b6
Author: Mikhnenko Sasha <78651190+4JustMe4 at users.noreply.github.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M clang/docs/LibASTMatchersReference.html
M clang/include/clang/ASTMatchers/ASTMatchers.h
Log Message:
-----------
Different info in docs in AST methods (#112190)
[Here](https://github.com/llvm/llvm-project/blob/6a98c4a1602591c942f01dceb3aa29ffd4cf1e5b/clang/include/clang/ASTMatchers/ASTMatchers.h#L4188-L4203)
and
[here](https://github.com/llvm/llvm-project/blob/6a98c4a1602591c942f01dceb3aa29ffd4cf1e5b/clang/include/clang/ASTMatchers/ASTMatchers.h#L3679-L3695)
we can see similar code samples and same examples:
```
cxxMemberCallExpr(on(callExpr()))
```
In the first case, it is
[written](https://github.com/llvm/llvm-project/blob/6a98c4a1602591c942f01dceb3aa29ffd4cf1e5b/clang/include/clang/ASTMatchers/ASTMatchers.h#L4201)
that the object must not be matched:
```
/// cxxMemberCallExpr(on(callExpr()))
/// does not match `(g()).m()`, because the parens are not ignored.
```
In the second case, it is
[written](https://github.com/llvm/llvm-project/blob/6a98c4a1602591c942f01dceb3aa29ffd4cf1e5b/clang/include/clang/ASTMatchers/ASTMatchers.h#L3693)
that the object must be matched:
```
/// cxxMemberCallExpr(on(callExpr()))
/// matches `(g()).m()`.
```
I think that parens are ignored
Commit: ea796e5237afbbef396b21ac04d4f32557c8db61
https://github.com/llvm/llvm-project/commit/ea796e5237afbbef396b21ac04d4f32557c8db61
Author: VladiKrapp-Arm <vladi.krapp at arm.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
Log Message:
-----------
[ARM] Prefer MUL to MULS on some implementations (#112540)
MULS adversely affects performance on many implementations. Where this
is the case, we prefer not to shrink MUL to MULS.
Commit: d9cd6072000488a80ba1c602f16a65055c594e0f
https://github.com/llvm/llvm-project/commit/d9cd6072000488a80ba1c602f16a65055c594e0f
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
Log Message:
-----------
[InstCombine] Add tests for #110919 (NFC)
Commit: c1047ba8366a447b61f845048a5f287dae24d9d0
https://github.com/llvm/llvm-project/commit/c1047ba8366a447b61f845048a5f287dae24d9d0
Author: Prashant Kumar <pk5561 at gmail.com>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
Log Message:
-----------
[MLIR] Enable pattern only for scf.forall op (#110230)
The init args shape might change in the loop body and hence the pattern
doesn't hold true.
Commit: 999df5a74c018169b4b8600914929d10eb055405
https://github.com/llvm/llvm-project/commit/999df5a74c018169b4b8600914929d10eb055405
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-10-17 (Thu, 17 Oct 2024)
Changed paths:
M bolt/lib/Passes/LongJmp.cpp
A bolt/test/AArch64/split-funcs-lite.s
M clang-tools-extra/include-cleaner/test/tool.cpp
M clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.rst
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/Basic/AArch64SVEACLETypes.def
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/IntegralAP.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/Type.cpp
M clang/lib/CodeGen/CGVTT.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/Parse/ParseInit.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/AST/ast-dump-aarch64-sve-types.c
M clang/test/CodeGen/aarch64-sve.c
A clang/test/CodeGen/sanitize-coverage-gated-callbacks.c
M clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
M clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
M clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp
M clang/test/CodeGenObjC/aarch64-sve-types.m
M clang/test/Driver/aarch64-v96a.c
M clang/test/Driver/hip-include-path.hip
M clang/test/Driver/hip-runtime-libs-msvc.hip
M clang/test/Driver/print-supported-extensions-aarch64.c
M clang/test/Modules/no-external-type-id.cppm
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-sve-types.c
A clang/test/Sema/aarch64-vcmla-undef.c
A clang/test/Sema/arm-mfp8.cpp
M clang/test/Sema/constexpr.c
M clang/test/SemaHLSL/resource_binding_attr_error_udt.hlsl
M clang/test/SemaObjC/aarch64-sve-types.m
M clang/utils/TableGen/SveEmitter.cpp
M compiler-rt/lib/fuzzer/FuzzerExtFunctionsWindows.cpp
M compiler-rt/lib/lsan/lsan_common.cpp
M compiler-rt/lib/profile/InstrProfilingMerge.c
M compiler-rt/lib/sanitizer_common/tests/sanitizer_posix_test.cpp
M compiler-rt/test/ubsan/TestCases/Misc/Posix/ubsan_options.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/optional.fir
M lldb/docs/index.rst
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
A lldb/test/API/tools/lldb-dap/send-event/Makefile
A lldb/test/API/tools/lldb-dap/send-event/TestDAP_sendEvent.py
A lldb/test/API/tools/lldb-dap/send-event/main.c
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/debugserver/source/libdebugserver.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/README.md
M lldb/tools/lldb-dap/lldb-dap.cpp
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/APFixedPoint.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/Transforms/Utils/Instrumentation.h
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetOptionsImpl.cpp
M llvm/lib/ExecutionEngine/MCJIT/MCJIT.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/Support/APInt.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMCallingConv.td
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.h
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/ValueTracking/non-negative-phi-bits.ll
M llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
M llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll
M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
M llvm/test/CodeGen/ARM/atomic-load-store.ll
M llvm/test/CodeGen/ARM/call-tc.ll
M llvm/test/CodeGen/ARM/debug-frame.ll
M llvm/test/CodeGen/ARM/ehabi.ll
M llvm/test/CodeGen/ARM/fast-isel-frameaddr.ll
M llvm/test/CodeGen/ARM/frame-chain.ll
M llvm/test/CodeGen/ARM/ifcvt5.ll
M llvm/test/CodeGen/ARM/ldrd.ll
M llvm/test/CodeGen/ARM/stack-frame-layout-remarks.ll
M llvm/test/CodeGen/ARM/stack-size-section.ll
M llvm/test/CodeGen/ARM/swifterror.ll
M llvm/test/CodeGen/ARM/v7k-abi-align.ll
M llvm/test/CodeGen/Thumb/frame-chain.ll
M llvm/test/CodeGen/Thumb2/avoidmuls.mir
M llvm/test/CodeGen/Thumb2/frame-pointer.ll
M llvm/test/CodeGen/Thumb2/frameless.ll
M llvm/test/CodeGen/Thumb2/frameless2.ll
M llvm/test/CodeGen/Thumb2/machine-licm.ll
A llvm/test/CodeGen/Thumb2/pacbti-m-frame-chain.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-extend.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/prefer-avx256-mulo.ll
M llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/MC/ARM/vlstm-vlldm-diag.s
M llvm/test/MC/ARM/vscclrm-asm.s
M llvm/test/MC/Disassembler/ARM/vscclrm.txt
M llvm/test/Transforms/InstCombine/call-guard.ll
M llvm/test/Transforms/InstCombine/cast_phi.ll
M llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
M llvm/test/Transforms/InstCombine/eq-of-parts.ll
M llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll
M llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll
M llvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll
M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
M llvm/test/Transforms/InstCombine/icmp-mul.ll
M llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
M llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll
M llvm/test/Transforms/InstCombine/icmp-range.ll
M llvm/test/Transforms/InstCombine/icmp-shr.ll
M llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-vscale.ll
M llvm/test/Transforms/InstCombine/icmp.ll
M llvm/test/Transforms/InstCombine/icmp_sdiv_with_and_without_range.ll
M llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
M llvm/test/Transforms/InstCombine/ispow2.ll
M llvm/test/Transforms/InstCombine/load-bitcast-select.ll
M llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/memchr.ll
M llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll
M llvm/test/Transforms/InstCombine/pr100298.ll
M llvm/test/Transforms/InstCombine/pr63791.ll
M llvm/test/Transforms/InstCombine/rem.ll
M llvm/test/Transforms/InstCombine/remove-loop-phi-multiply-by-zero.ll
M llvm/test/Transforms/InstCombine/strchr-1.ll
M llvm/test/Transforms/InstCombine/sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
A llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/simple_early_exit.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
M llvm/test/Transforms/PhaseOrdering/X86/ctlz-loop.ll
M llvm/test/Transforms/PhaseOrdering/gvn-replacement-vs-hoist.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected
M llvm/unittests/ADT/APFixedPointTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M mlir/include/mlir/Dialect/Arith/Transforms/Passes.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/IR/MLIRContext.h
M mlir/lib/Dialect/Arith/Transforms/EmulateNarrowType.cpp
M mlir/lib/Dialect/Arith/Transforms/UnsignedWhenEquivalent.cpp
M mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp
M mlir/lib/Dialect/MemRef/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/test/Conversion/VectorToLLVM/vector-xfer-to-llvm.mlir
M mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir
M mlir/test/Dialect/MemRef/emulate-narrow-type.mlir
M mlir/test/Dialect/MemRef/emulate-wide-int.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
M polly/lib/CodeGen/LoopGeneratorsKMP.cpp
Log Message:
-----------
Merge branch 'main' into users/shiltian/autogen-andorbitset
Compare: https://github.com/llvm/llvm-project/compare/4bd5d5d786f4...999df5a74c01
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