[all-commits] [llvm/llvm-project] 095d49: [InstCombine] Set `samesign` when converting signe...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 095d49da76be09143582e07a807c86d3b4334dec
      https://github.com/llvm/llvm-project/commit/095d49da76be09143582e07a807c86d3b4334dec
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-10-17 (Thu, 17 Oct 2024)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
    M llvm/test/Analysis/ValueTracking/non-negative-phi-bits.ll
    M llvm/test/Transforms/InstCombine/call-guard.ll
    M llvm/test/Transforms/InstCombine/cast_phi.ll
    M llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
    M llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll
    M llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll
    M llvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll
    M llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
    M llvm/test/Transforms/InstCombine/icmp-mul.ll
    M llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
    M llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll
    M llvm/test/Transforms/InstCombine/icmp-range.ll
    M llvm/test/Transforms/InstCombine/icmp-shr.ll
    M llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
    M llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
    M llvm/test/Transforms/InstCombine/icmp-vscale.ll
    M llvm/test/Transforms/InstCombine/icmp.ll
    M llvm/test/Transforms/InstCombine/icmp_sdiv_with_and_without_range.ll
    M llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
    M llvm/test/Transforms/InstCombine/ispow2.ll
    M llvm/test/Transforms/InstCombine/load-bitcast-select.ll
    M llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
    M llvm/test/Transforms/InstCombine/memchr.ll
    M llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll
    M llvm/test/Transforms/InstCombine/pr100298.ll
    M llvm/test/Transforms/InstCombine/pr63791.ll
    M llvm/test/Transforms/InstCombine/rem.ll
    M llvm/test/Transforms/InstCombine/remove-loop-phi-multiply-by-zero.ll
    M llvm/test/Transforms/InstCombine/strchr-1.ll
    M llvm/test/Transforms/InstCombine/sub.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
    M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
    M llvm/test/Transforms/PhaseOrdering/X86/ctlz-loop.ll
    M llvm/test/Transforms/PhaseOrdering/gvn-replacement-vs-hoist.ll

  Log Message:
  -----------
  [InstCombine] Set `samesign` when converting signed predicates into unsigned (#112642)

Alive2: https://alive2.llvm.org/ce/z/6cqdt-



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