[all-commits] [llvm/llvm-project] ad45eb: [ARM] Fix problems with register list in vscclrm (...

[John Brawn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ad45eb4a9c74a878998efe8fd734f5ae7af5003d
      https://github.com/llvm/llvm-project/commit/ad45eb4a9c74a878998efe8fd734f5ae7af5003d
  Author: John Brawn <john.brawn at arm.com>
  Date:   2024-10-17 (Thu, 17 Oct 2024)

  Changed paths:
    M llvm/lib/Target/ARM/ARMRegisterInfo.td
    M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
    M llvm/test/MC/ARM/vlstm-vlldm-diag.s
    M llvm/test/MC/ARM/vscclrm-asm.s
    M llvm/test/MC/Disassembler/ARM/vscclrm.txt

  Log Message:
  -----------
  [ARM] Fix problems with register list in vscclrm (#111825)

The register list in vscclrm is unusual in three ways:
 * The encoded size can be zero, meaning the list contains only vpr.
* Double-precision registers past d15 are permitted even when the
subtarget doesn't have them, they are instead ignored when the
instruction executes.
* The single-precision variant allows double-precision registers d16
onwards, which are encoded as a pair of single-precision registers.

Fixing this also incidentally changes a vlldm/vlstm error message: when
the first register is in the range d16-d31 we now get the "operand must
be exactly..." error instead of "register expected".



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