[all-commits] [llvm/llvm-project] a24c46: [MLIR] Fix assert expressions (#112474)

[Alexander Pivovarov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a24c468782010e17563f6aa93c5bb173c7f873b2
      https://github.com/llvm/llvm-project/commit/a24c468782010e17563f6aa93c5bb173c7f873b2
  Author: Alexander Pivovarov <pivovaa at amazon.com>
  Date:   2024-10-16 (Wed, 16 Oct 2024)

  Changed paths:
    M mlir/lib/Analysis/FlatLinearValueConstraints.cpp
    M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
    M mlir/lib/Dialect/Tensor/Utils/Utils.cpp

  Log Message:
  -----------
  [MLIR] Fix assert expressions (#112474)

I noticed that several assertions in MLIR codebase have issues with
operator precedence

The issue with operator precedence in these assertions is due to the way
logical operators are evaluated. The `&&` operator has higher precedence
than the `||` operator, which means the assertion is currently
evaluating incorrectly, like this:
```
assert((resType.getNumDynamicDims() == dynOutDims.size()) ||
       (dynOutDims.empty() && "Either none or all output dynamic dims must be specified!"));
```

We should add parentheses around the entire expression involving
`dynOutDims.empty()` to ensure that the logical conditions are grouped
correctly. Here’s the corrected version:
```
assert(((resType.getNumDynamicDims() == dynOutDims.size()) || dynOutDims.empty()) &&
       "Either none or all output dynamic dims must be specified!");

```



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