[all-commits] [llvm/llvm-project] fca651: [CodeGen][NewPM] Port EarlyIfConversion pass to NPM.

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/users/cdevadas/port-early-if-converter-to-npm
  Home:   https://github.com/llvm/llvm-project
  Commit: fca651c961f26d8c605eb050bdc145784582f24a
      https://github.com/llvm/llvm-project/commit/fca651c961f26d8c605eb050bdc145784582f24a
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2024-10-16 (Wed, 16 Oct 2024)

  Changed paths:
    A llvm/include/llvm/CodeGen/EarlyIfConversion.h
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Passes/CodeGenPassBuilder.h
    M llvm/include/llvm/Passes/MachinePassRegistry.def
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Passes/PassBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
    M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    M llvm/test/CodeGen/AArch64/early-ifcvt-likely-predictable.mir
    M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
    M llvm/test/CodeGen/AArch64/early-ifcvt-same-value.mir
    M llvm/test/CodeGen/PowerPC/early-ifcvt-no-isel.mir

  Log Message:
  -----------
  [CodeGen][NewPM] Port EarlyIfConversion pass to NPM.


  Commit: ea1940ef377f6a528795862816a079d92a59d2ad
      https://github.com/llvm/llvm-project/commit/ea1940ef377f6a528795862816a079d92a59d2ad
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2024-10-16 (Wed, 16 Oct 2024)

  Changed paths:
    M llvm/include/llvm/Passes/MachinePassRegistry.def

  Log Message:
  -----------
  made MF pass entry in alphabetic order.


Compare: https://github.com/llvm/llvm-project/compare/663c681e743b...ea1940ef377f

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