[all-commits] [llvm/llvm-project] d74143: [MLIR][ROCDL] Added `SchedGroupBarrier` and `IglpO...

[ravil-mobile via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d741435d776a1381bfb0d588f912c7ee7819d921
      https://github.com/llvm/llvm-project/commit/d741435d776a1381bfb0d588f912c7ee7819d921
  Author: ravil-mobile <ravil.aviva.com at gmail.com>
  Date:   2024-10-15 (Tue, 15 Oct 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/test/Dialect/LLVMIR/rocdl.mlir
    M mlir/test/Target/LLVMIR/rocdl.mlir

  Log Message:
  -----------
  [MLIR][ROCDL] Added `SchedGroupBarrier` and `IglpOpt` ops (#112237)

This PR adds missing `sched.group.barrier` and `rocdl.iglp.opt` ops to
the ROCDL dialect (see
[here](https://github.com/llvm/llvm-project/blob/ec78f0da0e9b1b8e2b2323e434ea742e272dd913/clang/include/clang/Basic/BuiltinsAMDGPU.def#L66-L68)).
The ops are converted to the corresponding intrinsic calls during the
translation from MLIR to LLVM IRs. This intrinsics are hints to the
instruction scheduler of the AMDGPU backend.



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