[all-commits] [llvm/llvm-project] f6c232: [RISCV] Promote fixed-length bf16 arith vector ops...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6c23222a4fe7291a7464460216aaad8f778947b
      https://github.com/llvm/llvm-project/commit/f6c23222a4fe7291a7464460216aaad8f778947b
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-10-15 (Tue, 15 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

  Log Message:
  -----------
  [RISCV] Promote fixed-length bf16 arith vector ops with zvfbfmin (#112393)

The aim is to have the same set of promotions on fixed-length bf16
vectors as on fixed-length f16 vectors, and then deduplicate them
similarly to what was done for scalable vectors.

It looks like fneg/fabs/fcopysign end up getting expanded because fsub
is now legal, and the default operation action must be expand.



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