[all-commits] [llvm/llvm-project] ae7751: [RISCV][VCIX] Add a tied constraint between rd and...

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ae7751f4050d5cbd3552adbcf9958600072d37ed
      https://github.com/llvm/llvm-project/commit/ae7751f4050d5cbd3552adbcf9958600072d37ed
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2024-10-14 (Mon, 14 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll

  Log Message:
  -----------
  [RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (#111630)

The instruction has the constraint, but the pseudo instruction is
missing.



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