[all-commits] [llvm/llvm-project] 1c1748: [RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRA...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c17484e107523af2583dd62537902202ce8f2e7
      https://github.com/llvm/llvm-project/commit/1c17484e107523af2583dd62537902202ce8f2e7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-10-14 (Mon, 14 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td

  Log Message:
  -----------
  [RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRAI64_HINT. (#112250)

c.srli(64) and c.srai(64) are encoded differently than c.slli(64). The
former have a 3-bit register, while the latter has a 5-bit register.
c.srli and c.srai already use RVInst16CB.

The "let Inst{11-10} =" prevented this from causing any functional
issues by dropping the upper 2 bits of the register. The ins/outs list
uses GPRC so the register class is constrained.



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