[all-commits] [llvm/llvm-project] dba54f: [RISCV] Add support for inline asm constraint vd (...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dba54fb074af1573984807e23640a202e0984a56
      https://github.com/llvm/llvm-project/commit/dba54fb074af1573984807e23640a202e0984a56
  Author: Jim Lin <jim at andestech.com>
  Date:   2024-10-14 (Mon, 14 Oct 2024)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll

  Log Message:
  -----------
  [RISCV] Add support for inline asm constraint vd (#111653)

It constrains vector registers excluding v0. Refer to
https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html RISC-V part.

This patch also adds a testcase for constraints vr, vd and vm.



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