[all-commits] [llvm/llvm-project] f5ff8e: Add signext

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-add-tests-for-memcmp-expansion
  Home:   https://github.com/llvm/llvm-project
  Commit: f5ff8e0be354cc1236057889189c3982b2513e0d
      https://github.com/llvm/llvm-project/commit/f5ff8e0be354cc1236057889189c3982b2513e0d
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-10-12 (Sat, 12 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
    M llvm/test/CodeGen/RISCV/memcmp.ll

  Log Message:
  -----------
  Add signext

Created using spr 1.3.6-beta.1



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