[all-commits] [llvm/llvm-project] 2c01b2: [ORC] Introduce RedirectionManager interface and i...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Oct 11 13:25:00 PDT 2024
Branch: refs/heads/users/alexey-bataev/spr/slpinitial-support-for-interleaved-loads
Home: https://github.com/llvm/llvm-project
Commit: 2c01b278580212914ec037bb5dd9b73702dfe7f1
https://github.com/llvm/llvm-project/commit/2c01b278580212914ec037bb5dd9b73702dfe7f1
Author: Sunho Kim <ksunhokim123 at gmail.com>
Date: 2024-10-12 (Sat, 12 Oct 2024)
Changed paths:
A llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
A llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
A llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
A llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp
Log Message:
-----------
[ORC] Introduce RedirectionManager interface and implementation using JITLink.
Commit: 04af63b267c391a4b0a0fb61060f724f8b5bc2be
https://github.com/llvm/llvm-project/commit/04af63b267c391a4b0a0fb61060f724f8b5bc2be
Author: Sunho Kim <ksunhokim123 at gmail.com>
Date: 2024-10-12 (Sat, 12 Oct 2024)
Changed paths:
M llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h
M llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp
M llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h
A llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp
A llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/tools/lli/lli.cpp
Log Message:
-----------
[ORC] Introduce IRPartitionLayer for common partition functionality.
Commit: 188ede28e046c911cb8e604fd1adc2b5cc1f264b
https://github.com/llvm/llvm-project/commit/188ede28e046c911cb8e604fd1adc2b5cc1f264b
Author: Sunho Kim <ksunhokim123 at gmail.com>
Date: 2024-10-12 (Sat, 12 Oct 2024)
Changed paths:
M compiler-rt/lib/orc/common.h
M compiler-rt/lib/orc/elfnix_platform.cpp
M llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
A llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
A llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
M llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp
A llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
Log Message:
-----------
[ORC] Implement basic reoptimization.
Commit: 03447ab98d33ad946fcffe212eb3235b41d09b59
https://github.com/llvm/llvm-project/commit/03447ab98d33ad946fcffe212eb3235b41d09b59
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
A llvm/test/CodeGen/X86/vector-shift-lut.ll
Log Message:
-----------
[X86] Add test coverage for #110317
Add tests showing potential to use PSHUFB for shifts of constant uniform values by using a pre-computed LUT of all legal shift amounts
Commit: 64bcb27d97137a1fd4f2f85025d414201c67b2d2
https://github.com/llvm/llvm-project/commit/64bcb27d97137a1fd4f2f85025d414201c67b2d2
Author: Caio Oliveira <caio.oliveira at intel.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M mlir/utils/spirv/gen_spirv_dialect.py
Log Message:
-----------
[mlir][spirv] Make gen_spirv_dialect.py more precise when finding inst_category (#111777)
Use a word boundary, current code was currently failing when parsing the
definition of because it would also match
`CooperativeMatrixOp` from a later mention of
`SPIRV_KHR_CooperativeMatrixOperandsAttr`.
Commit: 697d65ded678f405b637e769f1b0bcc755c8461a
https://github.com/llvm/llvm-project/commit/697d65ded678f405b637e769f1b0bcc755c8461a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Lower/OpenMP/Todo/map-modifiers-close.f90
A flang/test/Lower/OpenMP/Todo/map-modifiers-ompxhold.f90
A flang/test/Lower/OpenMP/Todo/map-modifiers-present.f90
A flang/test/Parser/OpenMP/map-modifiers.f90
A flang/test/Semantics/OpenMP/map-modifiers.f90
Log Message:
-----------
[flang][OpenMP] Parsing support for map type modifiers (#111860)
This commit adds parsing of type modifiers for the MAP clause: CLOSE,
OMPX_HOLD, and PRESENT. The support for ALWAYS has already existed.
The new modifiers are not yet handled in lowering: when present, a TODO
message is emitted and compilation stops.
Commit: 222d8fadb458d9b27c27e3314337ac3771b1d33b
https://github.com/llvm/llvm-project/commit/222d8fadb458d9b27c27e3314337ac3771b1d33b
Author: Sunho Kim <ksunhokim123 at gmail.com>
Date: 2024-10-12 (Sat, 12 Oct 2024)
Changed paths:
M llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp
Log Message:
-----------
[ORC] Try to skip unsupported targets in reoptimization test.
Many build bots are getting failures because of this:
https://lab.llvm.org/buildbot/#/builders/140/builds/8600
https://lab.llvm.org/buildbot/#/builders/137/builds/6824
https://lab.llvm.org/buildbot/#/builders/140/builds/8600
Commit: 7fea5c034ca1e08403da39d64f20b08a6e7542bd
https://github.com/llvm/llvm-project/commit/7fea5c034ca1e08403da39d64f20b08a6e7542bd
Author: Sunho Kim <ksunhokim123 at gmail.com>
Date: 2024-10-12 (Sat, 12 Oct 2024)
Changed paths:
M llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
Log Message:
-----------
[ORC] Try to skip unsupported targets in another reoptimization test.
Skipping another reoptimization test when target is not found.
Commit: 756ef97eeb7fccd45d1120023f6489961a4f8938
https://github.com/llvm/llvm-project/commit/756ef97eeb7fccd45d1120023f6489961a4f8938
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 04af63b267c3
Commit: 4ef737a43e1677626ec2c2f1c024472dde3051b9
https://github.com/llvm/llvm-project/commit/4ef737a43e1677626ec2c2f1c024472dde3051b9
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Utility/BUILD.gn
Log Message:
-----------
[gn build] Port 089227feaf0e
Commit: 91627546cdc22467d65884f67009f559739b16b1
https://github.com/llvm/llvm-project/commit/91627546cdc22467d65884f67009f559739b16b1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 188ede28e046
Commit: 7f1b465c6ae476e59dc90652d58fc648932d23b1
https://github.com/llvm/llvm-project/commit/7f1b465c6ae476e59dc90652d58fc648932d23b1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 2c01b2785802
Commit: 2aa1dbf9c92e3b27954ba9166c927616625073e8
https://github.com/llvm/llvm-project/commit/2aa1dbf9c92e3b27954ba9166c927616625073e8
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/unittests/SandboxIR/RegionTest.cpp
Log Message:
-----------
[SandboxIR] Add a test for creating non-contiguous Regions. (#112027)
It checks that a Region can have non-contiguous instructions, and that
when iterating through it you don't get the instructions in-between that
aren't part of the Region.
Commit: 48bda00b281a432d6de5e5e5dde6c5d66b992ac8
https://github.com/llvm/llvm-project/commit/48bda00b281a432d6de5e5e5dde6c5d66b992ac8
Author: Sirraide <aeternalmail at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ComputeDependence.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks.mm
A clang/test/SemaCXX/block-packs.cpp
Log Message:
-----------
[Clang] [Sema] Don't crash on unexpanded pack in invalid block literal (#110762)
Consider #109148:
```c++
template <typename ...Ts>
void f() {
[] {
(^Ts);
};
}
```
When we encounter `^Ts`, we try to parse a block and subsequently call
`DiagnoseUnexpandedParameterPack()` (in `ActOnBlockArguments()`), which
sees `Ts` and sets `ContainsUnexpandedParameterPack` to `true` in the
`LambdaScopeInfo` of the enclosing lambda. However, the entire block is
subsequently discarded entirely because it isn’t even syntactically
well-formed. As a result, `ContainsUnexpandedParameterPack` is `true`
despite the lambda’s body no longer containing any unexpanded packs,
which causes an assertion the next time
`DiagnoseUnexpandedParameterPack()` is called.
This pr moves handling of unexpanded parameter packs into
`CapturingScopeInfo` instead so that the same logic is used for both
blocks and lambdas. This fixes this issue since the
`ContainsUnexpandedParameterPack` flag is now part of the block (and
before that, its `CapturingScopeInfo`) and no longer affects the
surrounding lambda directly when the block is parsed. Moreover, this
change makes blocks actually usable with pack expansion.
This fixes #109148.
Commit: 2bb3d3a3f32ffaef3d9b6a27db7f1941f0cb1136
https://github.com/llvm/llvm-project/commit/2bb3d3a3f32ffaef3d9b6a27db7f1941f0cb1136
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
A clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/Modules/cxx-templates.cpp
Log Message:
-----------
Reapply "[Clang][Sema] Refactor collection of multi-level template argument lists (#106585, #111173)" (#111852)
This patch reapplies #111173, fixing a bug when instantiating dependent
expressions that name a member template that is later explicitly
specialized for a class specialization that is implicitly instantiated.
The bug is addressed by adding the `hasMemberSpecialization` function,
which return `true` if _any_ redeclaration is a member specialization.
This is then used when determining the instantiation pattern for a
specialization of a template, and when collecting template arguments for
a specialization of a template.
Commit: f0909e3a991c7b6515cafe2ce0a069a856fe675f
https://github.com/llvm/llvm-project/commit/f0909e3a991c7b6515cafe2ce0a069a856fe675f
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/Context.h
M llvm/include/llvm/SandboxIR/Utils.h
M llvm/unittests/SandboxIR/UtilsTest.cpp
Log Message:
-----------
[SandboxIR] Add utility function to find the base Value for Mem instructions (#112030)
Commit: bc53359b92e0fa3e1cf70505e1f2399f07c850d5
https://github.com/llvm/llvm-project/commit/bc53359b92e0fa3e1cf70505e1f2399f07c850d5
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
Update the C status page with papers adopted in Minneapolis
Commit: 31b85c6ead3e0e2979272046548f3ae8a51db289
https://github.com/llvm/llvm-project/commit/31b85c6ead3e0e2979272046548f3ae8a51db289
Author: vporpo <vporpodas at google.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Interval.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/IntervalTest.cpp
Log Message:
-----------
[SandboxVec][Interval] Implement Interval::comesBefore() (#112026)
This patch implements `Interval::comesBefore(const Interval &Other)`
which returns true if this interval is strictly before Other in program
order. The function asserts that the intervals are disjoint.
Commit: adaa603224fee842b4f71824617adb3b0c7d9cf1
https://github.com/llvm/llvm-project/commit/adaa603224fee842b4f71824617adb3b0c7d9cf1
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
A llvm/test/MachineVerifier/test_multiple_errors.mir
Log Message:
-----------
[MachineVerifier] Report errors from one thread at a time (#111605)
Create the `ReportedErrors` class to track the number of reported errors
during verification. The class will block reporting errors if some other
thread is currently reporting an error.
I've encountered a case where there were many different verifications
reporting errors at the same time on different threads. This ensures
that we don't start printing the error from one case until we are
completely done printing errors from other cases. Most of the time
`AbortOnError = true` so we usually abort after reporting the first
error.
Depends on https://github.com/llvm/llvm-project/pull/111602.
Commit: 58d97034c9c149d175c66440d31f46e9dfd4b760
https://github.com/llvm/llvm-project/commit/58d97034c9c149d175c66440d31f46e9dfd4b760
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M mlir/include/mlir/Conversion/OpenMPToLLVM/ConvertOpenMPToLLVM.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
Log Message:
-----------
[mlir][OpenMP] Implement the ConvertToLLVMPatternInterface (#101997)
This patch implements the `ConvertToLLVMPatternInterface` for the OpenMP
dialect, allowing `convert-to-llvm` to act on the OpenMP dialect.
Commit: cc8edbca7de9204915c84477b8c03a33abeb7775
https://github.com/llvm/llvm-project/commit/cc8edbca7de9204915c84477b8c03a33abeb7775
Author: vporpo <vporpodas at google.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Interval.h
Log Message:
-----------
[SandboxVec][Interval][NFC] Rename From/To to Top/Bottom (#112034)
The API was already using top()/bottom() but internally we were still
using From/To. This patch fixes this.
Top/Bottom seems a better choice because implies program order, whereas
From/To does not.
Commit: 2967e5f8007d873a3e9d97870d2461d0827a3976
https://github.com/llvm/llvm-project/commit/2967e5f8007d873a3e9d97870d2461d0827a3976
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-int.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/legalize-fneg.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/misched-load-clustering.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vadc.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn.ll
M llvm/test/CodeGen/RISCV/rvv/vasub.ll
M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/split-store.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
Log Message:
-----------
[RISCV] Enable store clustering by default (#73796)
Builds on #73789, enabling store clustering by default using the same
heuristic.
Commit: 77aa8257acbd773c0c430cd962da1bcfbd5ee94b
https://github.com/llvm/llvm-project/commit/77aa8257acbd773c0c430cd962da1bcfbd5ee94b
Author: Brian Cain <bcain at quicinc.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M lld/ELF/Arch/Hexagon.cpp
M lld/test/ELF/hexagon-shared.s
Log Message:
-----------
[lld][Hexagon] Support predicated-add GOT_16_X mask lookup (#111896)
When encountering an instruction like `if (p0) r0 = add(r0,##bar at GOT)`,
lld would fail with:
```
ld.lld: error: unrecognized instruction for 16_X type: 0x7400C000
```
This issue was encountered while building libreadline with clang 19.1.0.
Fixes: #111876
Commit: 16c8056ca9d3c28ca5e409162a0c82d5726ea655
https://github.com/llvm/llvm-project/commit/16c8056ca9d3c28ca5e409162a0c82d5726ea655
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
Log Message:
-----------
[AMDGPU][test] update test with update_mc_test_check (#111913)
a non-functional change
Update test script with update_mc_test_check script and sort the
testline to be alphabetic order. This helps to maintain the test file in
a clean state
Commit: 3ed8acf2f077fe250773f2ada986c7114adcbb85
https://github.com/llvm/llvm-project/commit/3ed8acf2f077fe250773f2ada986c7114adcbb85
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Simplify check for external user parent basic block, NFC.
Commit: 6baf2a3bfe39e6a2dce0e4ad01a12ee7fdd49d11
https://github.com/llvm/llvm-project/commit/6baf2a3bfe39e6a2dce0e4ad01a12ee7fdd49d11
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-10-11 (Fri, 11 Oct 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ComputeDependence.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/Sema/ScopeInfo.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/AST/ComputeDependence.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks.mm
A clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
A clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/Modules/cxx-templates.cpp
A clang/test/SemaCXX/block-packs.cpp
M clang/www/c_status.html
M compiler-rt/lib/orc/common.h
M compiler-rt/lib/orc/elfnix_platform.cpp
M flang/examples/FeatureList/FeatureList.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.h
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Lower/OpenMP/Todo/map-modifiers-close.f90
A flang/test/Lower/OpenMP/Todo/map-modifiers-ompxhold.f90
A flang/test/Lower/OpenMP/Todo/map-modifiers-present.f90
A flang/test/Parser/OpenMP/map-modifiers.f90
A flang/test/Semantics/OpenMP/map-modifiers.f90
M lld/ELF/Arch/Hexagon.cpp
M lld/test/ELF/hexagon-shared.s
M llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h
M llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp
M llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h
A llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h
A llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
A llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h
A llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h
M llvm/include/llvm/SandboxIR/Context.h
M llvm/include/llvm/SandboxIR/Utils.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Interval.h
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp
A llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp
A llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
A llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp
A llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/DependencyGraph.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-int.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/legalize-fneg.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/misched-load-clustering.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vadc.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vand.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn.ll
M llvm/test/CodeGen/RISCV/rvv/vasub.ll
M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/split-store.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
A llvm/test/CodeGen/X86/vector-shift-lut.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_promote.s
A llvm/test/MachineVerifier/test_multiple_errors.mir
M llvm/tools/lli/lli.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
A llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp
A llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
M llvm/unittests/SandboxIR/RegionTest.cpp
M llvm/unittests/SandboxIR/UtilsTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/IntervalTest.cpp
M llvm/utils/gn/secondary/lldb/source/Utility/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M mlir/include/mlir/Conversion/OpenMPToLLVM/ConvertOpenMPToLLVM.h
M mlir/include/mlir/InitAllExtensions.h
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
M mlir/utils/spirv/gen_spirv_dialect.py
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