[all-commits] [llvm/llvm-project] 2967e5: [RISCV] Enable store clustering by default (#73796)

Alex Bradbury via All-commits all-commits at lists.llvm.org
Fri Oct 11 12:26:15 PDT 2024 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2967e5f8007d873a3e9d97870d2461d0827a3976
      https://github.com/llvm/llvm-project/commit/2967e5f8007d873a3e9d97870d2461d0827a3976
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2024-10-11 (Fri, 11 Oct 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
    M llvm/test/CodeGen/RISCV/abds-neg.ll
    M llvm/test/CodeGen/RISCV/abds.ll
    M llvm/test/CodeGen/RISCV/abdu-neg.ll
    M llvm/test/CodeGen/RISCV/add-before-shl.ll
    M llvm/test/CodeGen/RISCV/alloca.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
    M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
    M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
    M llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
    M llvm/test/CodeGen/RISCV/calls.ll
    M llvm/test/CodeGen/RISCV/double-calling-conv.ll
    M llvm/test/CodeGen/RISCV/double-convert-strict.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
    M llvm/test/CodeGen/RISCV/fastcc-float.ll
    M llvm/test/CodeGen/RISCV/fastcc-half.ll
    M llvm/test/CodeGen/RISCV/fastcc-int.ll
    M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fp128.ll
    M llvm/test/CodeGen/RISCV/frame.ll
    M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/legalize-fneg.ll
    M llvm/test/CodeGen/RISCV/llvm.exp10.ll
    M llvm/test/CodeGen/RISCV/llvm.frexp.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/memset-inline.ll
    M llvm/test/CodeGen/RISCV/misched-load-clustering.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/nontemporal.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/pr63816.ll
    M llvm/test/CodeGen/RISCV/push-pop-popret.ll
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
    M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vadc.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vand.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
    M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vor.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor.ll
    M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/split-offsets.ll
    M llvm/test/CodeGen/RISCV/split-store.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/stack-slot-size.ll
    M llvm/test/CodeGen/RISCV/stack-store-check.ll
    M llvm/test/CodeGen/RISCV/tail-calls.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/RISCV/xtheadmempair.ll

  Log Message:
  -----------
  [RISCV] Enable store clustering by default (#73796)

Builds on #73789, enabling store clustering by default using the same
heuristic.



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