[all-commits] [llvm/llvm-project] 034837: [mlir][linalg] Introduce transpose semantic to 'li...
Md Asghar Ahmad Shahid via All-commits
all-commits at lists.llvm.org
Thu Oct 10 09:01:21 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 03483737a7a2d72a257a5ab6ff01748ad9cf0f75
https://github.com/llvm/llvm-project/commit/03483737a7a2d72a257a5ab6ff01748ad9cf0f75
Author: Md Asghar Ahmad Shahid <md.asghar.ahmad.shahid at intel.com>
Date: 2024-10-10 (Thu, 10 Oct 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
M mlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/TransposeMatmul.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/NVGPU/TransformOps/NVGPUTransformOps.cpp
M mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
M mlir/test/Dialect/Linalg/generalize-named-ops.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/named-ops.mlir
M mlir/test/python/dialects/linalg/ops.py
M mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
Log Message:
-----------
[mlir][linalg] Introduce transpose semantic to 'linalg.matmul' ops. (#104783)
The main goal of this patch is to extend the semantic of 'linalg.matmul'
named op to include per operand transpose semantic while also laying out
a way to move ops definition from OpDSL to tablegen. Hence, it is
implemented in tablegen. Transpose semantic is as follows.
By default 'linalg.matmul' behavior will remain as is. Transpose
semantics can be appiled on per input operand by specifying the optional
permutation attributes (namely 'permutationA' for 1st input and
'permutationB' for 2nd input) for each operand explicitly as needed. By
default, no transpose is mandated for any of the input operand.
Example:
```
%val = linalg.matmul ins(%arg0, %arg1 : memref<5x3xf32>,
memref<5x7xf32>)
outs(%arg2: memref<3x7xf32>)
permutationA = [1, 0]
permutationB = [0, 1]
```
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