[all-commits] [llvm/llvm-project] 44e768: [MIR] Serialize virtual register flags

[Akshat Oke via All-commits]

  Branch: refs/heads/users/Akshat-Oke/09-27-_mir_serialize_virtual_register_flags
  Home:   https://github.com/llvm/llvm-project
  Commit: 44e76830ad966df58449c0016f7ea2670186521e
      https://github.com/llvm/llvm-project/commit/44e76830ad966df58449c0016f7ea2670186521e
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MIRParser/MIParser.h
    M llvm/include/llvm/CodeGen/MIRYamlMapping.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
    M llvm/lib/CodeGen/MIRPrinter.cpp

  Log Message:
  -----------
  [MIR] Serialize virtual register flags


  Commit: cbbe63a51a87be9e493d287888c1076cf33d7b4f
      https://github.com/llvm/llvm-project/commit/cbbe63a51a87be9e493d287888c1076cf33d7b4f
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
    M llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
    M llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
    M llvm/test/CodeGen/MIR/X86/register-operand-class.mir
    M llvm/test/CodeGen/MIR/X86/roundtrip.mir
    M llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
    M llvm/test/CodeGen/MIR/X86/virtual-registers.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-inc.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir
    M llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir

  Log Message:
  -----------
  Update tests


  Commit: bf2f93280d0e39a56a38fae667a734c9df78de6e
      https://github.com/llvm/llvm-project/commit/bf2f93280d0e39a56a38fae667a734c9df78de6e
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MIRParser/MIParser.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MIRParser/MIRParser.cpp

  Log Message:
  -----------
  clang-format


  Commit: 233d54c530f9fad56954cada83eb4509eee5ffa2
      https://github.com/llvm/llvm-project/commit/233d54c530f9fad56954cada83eb4509eee5ffa2
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MIRParser/MIParser.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MIRPrinter.cpp

  Log Message:
  -----------
  SmallString, std::optional, enum : uint8_t


  Commit: cf4a38ba9a665d801aee96a5196137067ae10c2f
      https://github.com/llvm/llvm-project/commit/cf4a38ba9a665d801aee96a5196137067ae10c2f
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    A llvm/test/CodeGen/MIR/Generic/register-flag-error.mir

  Log Message:
  -----------
  Add failing test


  Commit: d12787e908731b47fe0e90eb5b671b040797a96d
      https://github.com/llvm/llvm-project/commit/d12787e908731b47fe0e90eb5b671b040797a96d
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/test/CodeGen/MIR/Generic/register-flag-error.mir

  Log Message:
  -----------
  AS


  Commit: 6296d6cefd0fdf25006b1cf7a6526e7e7c2a503f
      https://github.com/llvm/llvm-project/commit/6296d6cefd0fdf25006b1cf7a6526e7e7c2a503f
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp

  Log Message:
  -----------
  Moving the noteNewVirtualRegister change to a new commit


  Commit: 7af9e5eb6fb66d06d2b5088ee147816925643c29
      https://github.com/llvm/llvm-project/commit/7af9e5eb6fb66d06d2b5088ee147816925643c29
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-10-09 (Wed, 09 Oct 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/MIRPrinter.cpp

  Log Message:
  -----------
  StringLiteral


Compare: https://github.com/llvm/llvm-project/compare/9f8b6ebaf2ec...7af9e5eb6fb6

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