[all-commits] [llvm/llvm-project] 5cb6b1: [AMDGPU] Constrain use LiveMask by the operand's L...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cb6b15568c1554a2ea89fee849ed0e27b785ee0
      https://github.com/llvm/llvm-project/commit/5cb6b15568c1554a2ea89fee849ed0e27b785ee0
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2024-10-08 (Tue, 08 Oct 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
    M llvm/lib/Target/AMDGPU/GCNRegPressure.h

  Log Message:
  -----------
  [AMDGPU] Constrain use LiveMask by the operand's LaneMask for RP calculation.

For speculative RP queries, recede may calculate inaccurate masks for subreg uses. Previously, the calculation would look at any live lane for the use at the position of the MI in the LIS. This also adds lanes for any subregs which are live at but not used by the instruction. By constraining against the getSubRegIndexLaneMask for the operand's subreg, we are sure to not pick up on these extra lanes.

For current clients of recede, this is not an issue. This is because 1. the current clients do not violate the program order in the LIS, and 2. the change to RP is based on the difference between previous mask and new mask. Since current clients are not exposed to this issue, this patch is sort of NFC.

Co-authored-by: Valery Pykhtin Valery.Pykhtin at amd.com
Change-Id: Iaed80271226b2587297e6fb78fe081afec1a9275



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