[all-commits] [llvm/llvm-project] f93f92: [RISCV][MC] Support Assembling 48- and 64-bit Inst...

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f93f925d4f3b9505eecf02097713003d3cf4b6fa
      https://github.com/llvm/llvm-project/commit/f93f925d4f3b9505eecf02097713003d3cf4b6fa
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2024-10-08 (Tue, 08 Oct 2024)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/MC/RISCV/insn-invalid.s
    M llvm/test/MC/RISCV/insn.s
    M llvm/test/MC/RISCV/insn_c-invalid.s

  Log Message:
  -----------
  [RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)

This adds `.insn` support for assembling instructions of 48- and
64-bits (only when giving an explicit length). Disassembly already
knows to bunch up the instruction bits for these instructions.

This changes some error messages so they are a little clearer.

Co-authored-by: Sudharsan Veeravalli <quic_svs at quicinc.com>



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