[all-commits] [llvm/llvm-project] 9f255d: [AArch64][GlobalISel] Lower fp16 abs and neg witho...

David Green via All-commits all-commits at lists.llvm.org
Thu Sep 26 23:44:19 PDT 2024


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f255d863f31f3d3c434f662dc9e2255ef54407c
      https://github.com/llvm/llvm-project/commit/9f255d863f31f3d3c434f662dc9e2255ef54407c
  Author: David Green <david.green at arm.com>
  Date:   2024-09-27 (Fri, 27 Sep 2024)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
    M llvm/test/CodeGen/AArch64/f16-instructions.ll
    M llvm/test/CodeGen/AArch64/fabs.ll
    M llvm/test/CodeGen/AArch64/fneg.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Lower fp16 abs and neg without fullfp16. (#110096)

This changes the existing promote logic to lower, so that it can use
normal integer operations. A minor change was needed to fneg lower code
to handle vectors.



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