[all-commits] [llvm/llvm-project] 8a7843: [RISCV] Add 16 bit GPR sub-register for Zhinx. (#1...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8a7843ca0ff56a2d5c22bc78ba16309d5af39869
      https://github.com/llvm/llvm-project/commit/8a7843ca0ff56a2d5c22bc78ba16309d5af39869
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-26 (Thu, 26 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
    M llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
    M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-imm.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/kcfi-mir.ll
    A llvm/test/CodeGen/RISCV/make-compressible-zbc-zhinx.mir

  Log Message:
  -----------
  [RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

This patches adds a 16 bit register class for use with Zhinx
instructions. This makes them more similar to Zfh instructions and
allows us to only spill 16 bits.

I've added CodeGenOnly instructions for load/store using GPRF16 as that
gave better results than insert_subreg/extract_subreg. I'm using FSGNJ
for GPRF16 copy with Zhinx as that gave better results. Zhinxmin will
use ADDI+subreg operations.

Function arguments use this new GPRF16 register class for f16 arguments
with Zhinxmin. Eliminating the need to use RISCVISD::FMV* nodes.

I plan to extend this idea to Zfinx next.



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