[all-commits] [llvm/llvm-project] a059b2: [SPIR-V] Allow intrinsics with aggregate return ty...

[Vyacheslav Levytskyy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a059b29930d046a2426be15c58421ee8971ec11c
      https://github.com/llvm/llvm-project/commit/a059b29930d046a2426be15c58421ee8971ec11c
  Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
  Date:   2024-09-26 (Thu, 26 Sep 2024)

  Changed paths:
    M llvm/docs/SPIRVUsage.rst
    M llvm/include/llvm/IR/IntrinsicsSPIRV.td
    M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
    M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
    M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
    M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
    M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
    M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
    M llvm/lib/Target/SPIRV/SPIRVUtils.h
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/smul.with.overflow.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll
    M llvm/test/CodeGen/SPIRV/llvm-intrinsics/umul.with.overflow.ll
    A llvm/test/CodeGen/SPIRV/llvm-intrinsics/usub.with.overflow.ll
    A llvm/test/CodeGen/SPIRV/optimizations/add-check-overflow.ll
    A llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll

  Log Message:
  -----------
  [SPIR-V] Allow intrinsics with aggregate return type to reach GlobalISel (#108893)

Two main goals of this PR are:
* to support "Arithmetic with Overflow" intrinsics, including the
special case when those intrinsics are being generated by the
CodeGenPrepare pass during translations with optimization;
* to redirect intrinsics with aggregate return type to be lowered via
GlobalISel operations instead of SPIRV-specific unfolding/lowering (see
https://github.com/llvm/llvm-project/pull/95012).

There is a new test case
`llvm/test/CodeGen/SPIRV/passes/translate-aggregate-uaddo.ll` that
describes and checks the general logics of the translation.

This PR continues a series of PRs aimed to identify and fix flaws in
code emission, to improve pass rates for the mode with expensive checks
set on (see https://github.com/llvm/llvm-project/pull/101732,
https://github.com/llvm/llvm-project/pull/104104,
https://github.com/llvm/llvm-project/pull/106966), having in mind the
ultimate goal of proceeding towards the non-experimental status of
SPIR-V Backend.

The reproducers are:

1) consider `llc -O3 -mtriple=spirv64-unknown-unknown ...` with:

```
define spir_func i32 @foo(i32 %a, ptr addrspace(4) %p) {
entry:
  br label %l1

l1:
  %e = phi i32 [ %a, %entry ], [ %i, %body ]
  %i = add nsw i32 %e, 1
  %fl = icmp eq i32 %i, 0
  br i1 %fl, label %exit, label %body

body:
  store i8 42, ptr addrspace(4) %p
  br label %l1

exit:
  ret i32 %i
}
```

2) consider `llc -O0 -mtriple=spirv64-unknown-unknown ...` with:

```
define spir_func i32 @foo(i32 %a, ptr addrspace(4) %p) {
entry:
  br label %l1

l1:                                               ; preds = %body, %entry
  %e = phi i32 [ %a, %entry ], [ %math, %body ]
  %0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %e, i32 1)
  %math = extractvalue { i32, i1 } %0, 0
  %ov = extractvalue { i32, i1 } %0, 1
  br i1 %ov, label %exit, label %body

body:                                             ; preds = %l1
  store i8 42, ptr addrspace(4) %p, align 1
  br label %l1

exit:                                             ; preds = %l1
  ret i32 %math
}
```



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