[all-commits] [llvm/llvm-project] f172c3: [RISCV] Lower memory ops and VP splat for zvfhmin ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f172c31a578fa72375ce7a2199ecdfbbd764dc0e
      https://github.com/llvm/llvm-project/commit/f172c31a578fa72375ce7a2199ecdfbbd764dc0e
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-26 (Thu, 26 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll

  Log Message:
  -----------
  [RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

We can lower f16/bf16 memory ops without promotion through the existing
custom lowering.

Some of the zero strided VP loads get combined to a VP splat, so we need
to also handle the lowering for that for f16/bf16 w/ zvfhmin/zvfbfmin.
This patch copies the lowering from ISD::SPLAT_VECTOR over to
lowerScalarSplat which is used by the VP splat lowering.



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