[all-commits] [llvm/llvm-project] 62f737: [Driver][X86] Add flang visibility for -m[no-]evex...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Tue Sep 24 19:48:19 PDT 2024
Branch: refs/heads/users/vitalybuka/spr/main.hwasan-check-order-of-mapping-flags
Home: https://github.com/llvm/llvm-project
Commit: 62f737f7409b5d2b33c746158c62f14e5bb78aed
https://github.com/llvm/llvm-project/commit/62f737f7409b5d2b33c746158c62f14e5bb78aed
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M flang/test/Driver/target-cpu-features.f90
Log Message:
-----------
[Driver][X86] Add flang visibility for -m[no-]evex512 (#109598)
The `-m[no-]evex512` are nontrivial options which are used to control
vector size of other AVX512 features. Hence we expose both to flang for
Fortran users.
Commit: 9ed46fbe9fa153316b7b0bb0906f3c8db45a8f81
https://github.com/llvm/llvm-project/commit/9ed46fbe9fa153316b7b0bb0906f3c8db45a8f81
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/Common/DriverDispatcher.cpp
M lld/ELF/Driver.cpp
M lld/MachO/InputSection.cpp
Log Message:
-----------
[lld] Use StringRef idioms (NFC) (#109584)
Commit: ba5e19580913d0b4cac249a81f0aabf7a0a3317f
https://github.com/llvm/llvm-project/commit/ba5e19580913d0b4cac249a81f0aabf7a0a3317f
Author: Shourya Goel <shouryagoel10000 at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/include/llvm-libc-macros/math-function-macros.h
M libc/test/include/CMakeLists.txt
A libc/test/include/IsSubnormalTest.h
A libc/test/include/issubnormal_test.c
A libc/test/include/issubnormal_test.cpp
A libc/test/include/issubnormalf_test.cpp
A libc/test/include/issubnormall_test.cpp
Log Message:
-----------
[libc][math] Implement issubnormal macro. (#109572)
#109201
Commit: 80cdc3718036cd3ee33424953821ac01046d5278
https://github.com/llvm/llvm-project/commit/80cdc3718036cd3ee33424953821ac01046d5278
Author: Thomas Fransham <tfransham at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/tools/CMakeLists.txt
Log Message:
-----------
[Clang] Include the clang-shlib CMake project when building for MSVC (#109457)
Enable building clang-cpp shared library for windows when building with
explicit visibility macros enabled and LLVM is built as a shared
library(LLVM_BUILD_LLVM_DYLIB_VIS).
This is part of the effort to support for enabling plugins on windows by
adding better support for building LLVM and Clang as a DLL.
Commit: c3d3cef8d58377b02032b07b5f094a402a70435a
https://github.com/llvm/llvm-project/commit/c3d3cef8d58377b02032b07b5f094a402a70435a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/test/MC/RISCV/rv64-relax-all.s
Log Message:
-----------
[RISCV] Don't delete all fixups in RISCVMCCodeEmitter::expandLongCondBr. (#109513)
The Fixups vector passed into this function may already have fixups in
it from earlier instructions. We should not erase those. We just want to
erase fixups added by this function.
Fixes #108612.
Commit: 80b44517f571689ede9327b3122caff3c631408e
https://github.com/llvm/llvm-project/commit/80b44517f571689ede9327b3122caff3c631408e
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
Log Message:
-----------
[RISCV][TTI] Add instruction cost for vp.select. (#109381)
This patch make instruction cost for vp.select the same as its non-vp
counterpart.
Commit: 5a4c6f97997f3cdfa9d98f7f0b546e331ee9cc4a
https://github.com/llvm/llvm-project/commit/5a4c6f97997f3cdfa9d98f7f0b546e331ee9cc4a
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/test/Transforms/SimplifyCFG/speculate-derefable-load.ll
Log Message:
-----------
[Loads] Check context instruction for context-sensitive derefability (#109277)
If a dereferenceability fact is provided through `!dereferenceable` (or
similar), it may only hold on the given control flow path. When we use
`isSafeToSpeculativelyExecute()` to check multiple instructions, we
might make use of `!dereferenceable` information that does not hold at
the speculation target. This doesn't happen when speculating
instructions one by one, because `!dereferenceable` will be dropped
while speculating.
Fix this by checking whether the instruction with `!dereferenceable`
dominates the context instruction. If this is not the case, it means we
are speculating, and cannot guarantee that it holds at the speculation
target.
Fixes https://github.com/llvm/llvm-project/issues/108854.
Commit: 8a6248b739d705577fa5414b4010605dca38aa79
https://github.com/llvm/llvm-project/commit/8a6248b739d705577fa5414b4010605dca38aa79
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
Log Message:
-----------
[SimplifyCFG] Don't separate a load/store from its gep during sinking (#102318)
If we can sink the a load/store, but not the gep producing its pointer
operand, don't sink the load/store either. This may prevent the gep from
being folded into an addressing mode, and may also negatively affect
further analysis.
Fixes https://github.com/llvm/llvm-project/issues/96838.
Commit: 84b1489c8f8d4fb3c541167301c29ee4dad1af78
https://github.com/llvm/llvm-project/commit/84b1489c8f8d4fb3c541167301c29ee4dad1af78
Author: David Green <david.green at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/CodeGen/ARM/vbsl.ll
Log Message:
-----------
[ARM] Update VBIC tests. NFC
Commit: df6855ba57b2cede7b1578e74276f3ad33c2ad5d
https://github.com/llvm/llvm-project/commit/df6855ba57b2cede7b1578e74276f3ad33c2ad5d
Author: Benji Smith <6193112+Benjins at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm-c/Core.h
M llvm/lib/IR/Core.cpp
M llvm/test/Bindings/llvm-c/atomics.ll
Log Message:
-----------
[C API] Add usub_cond and usub_sat atomic ops to C API (#109532)
These were added in the C++ API in
https://github.com/llvm/llvm-project/pull/105568 but were not exposed
via the C API previously
Commit: 6ad268e3913cb6814fabae420a8e80156e1632a7
https://github.com/llvm/llvm-project/commit/6ad268e3913cb6814fabae420a8e80156e1632a7
Author: dlav-sc <daniil.avdeev at syntacore.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/source/Target/Target.cpp
Log Message:
-----------
[lldb] refactor Target::Install function (#108996)
refactor Target::Install function
Commit: c8e0672864abf6fb624ddde5d6a1775d8634213a
https://github.com/llvm/llvm-project/commit/c8e0672864abf6fb624ddde5d6a1775d8634213a
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopConstrainer.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
M llvm/lib/Transforms/Utils/LoopVersioning.cpp
Log Message:
-----------
[Loops] Use forgetLcssaPhiWithNewPredecessor() in more places
Use the more aggressive invalidation method in a number of places
that add incoming values to lcssa phi nodes. It is likely that
it's possible to construct cases with incorrect SCEV preservation
similar to https://github.com/llvm/llvm-project/issues/109333 for
these.
Commit: 898fd396b836600ef857464941220d07894b859b
https://github.com/llvm/llvm-project/commit/898fd396b836600ef857464941220d07894b859b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/test/AST/ByteCode/new-delete.cpp
Log Message:
-----------
[clang][bytecode] Check allocation size limit for operator new (#109590)
Commit: 02711a77c0bf8b7921f48aaa601564449888e458
https://github.com/llvm/llvm-project/commit/02711a77c0bf8b7921f48aaa601564449888e458
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M compiler-rt/test/asan/TestCases/Linux/preinstalled_signal.cpp
Log Message:
-----------
[ASan][test] XFAIL Linux/preinstalled_signal.cpp on Linux/sparc64 (#109623)
With ASan testing enabled on SPARC as per PR #107405, the
```
AddressSanitizer-sparc-linux-dynamic :: TestCases/Linux/preinstalled_signal.cpp
```
test `FAIL`s on Linux/sparc64. See Issue #109573 for all the details,
but the core is that `syscall(__NR_rt_sigaction)` cannot be used because
it takes an additional argument that isn't accessible outside of `libc`,
while switching to `sigaction` instead changes the order of
`AsanInitInternal` and `Init`, breaking the test.
Therefore this patch `XFAIL`s the test.
Tested on `sparc64-unknown-linux-gnu` and `x86_64-pc-linux-gnu`.
Commit: db3569d2e5aa4d967a2e8c5b9893f9a49937e55d
https://github.com/llvm/llvm-project/commit/db3569d2e5aa4d967a2e8c5b9893f9a49937e55d
Author: Michal Rostecki <vadorovsky at protonmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/Bindings/llvm-c/debug_info_new_format.ll
M llvm/tools/llvm-c-test/main.c
Log Message:
-----------
[llvm-c-test] Rename --test-dibuilder-debuginfo-format to `--test-dibuilder` (#105702)
The former name was introduced during the split between debug info
intrinsic and `DbgRecord`. Before the split, it was named
`--test-dibuilder`.
However, the full migration to `DbgRecord` happened already and we have
just one test suite related to building debug info using LLVM-C API.
Therefore, it makes sense to rename it back to `--test-dibuilder`.
Commit: 8b4b7d28f7c344c728a9812aa99d9ad24edb40a2
https://github.com/llvm/llvm-project/commit/8b4b7d28f7c344c728a9812aa99d9ad24edb40a2
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] additional fix for 65bc259a97cd8cc70907b65f59aff728245ba9c0
Commit: b953914e2fef53773baa1fa89e96671015d45852
https://github.com/llvm/llvm-project/commit/b953914e2fef53773baa1fa89e96671015d45852
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Object/COFFObjectFile.cpp
M llvm/test/tools/llvm-readobj/COFF/arm64ec-chpe.yaml
Log Message:
-----------
[Object][COFF] Fix CHPE metadata offset check (#109591)
Commit: 6fc2451167ec991361dd0568de9a9fa2926f8da8
https://github.com/llvm/llvm-project/commit/6fc2451167ec991361dd0568de9a9fa2926f8da8
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning-execution-mode.s
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning.s
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
Log Message:
-----------
Reland "[llvm-exegesis] Add support for pinning benchmarking process to a CPU (#85168)"
This reverts commit 5e3d48a68096a0017a0fa4bb89f2d48767c8a7e4.
This relands commit 9886788a8a500a1b429a6db64397c849b112251c.
This was originally causing build failures on more esoteric platforms
that have different definitions of getcpu. This is only intended to be
supported on x86-64 currently, so just use preprocessor definitions to
special case the function.
Commit: 02ee96eca90741031a26f0f06cd48bb0ba558d1a
https://github.com/llvm/llvm-project/commit/02ee96eca90741031a26f0f06cd48bb0ba558d1a
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
M llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/ne-overflow.ll
M llvm/test/Analysis/ScalarEvolution/predicated-exit-count.ll
M llvm/test/Analysis/ScalarEvolution/predicated-symbolic-max-backedge-taken-count.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/simple_early_exit.ll
Log Message:
-----------
[Analysis] Teach isDereferenceableAndAlignedInLoop about SCEV predicates (#106562)
Currently if a loop contains loads that we can prove at compile time
are dereferenceable when certain conditions are satisfied the function
isDereferenceableAndAlignedInLoop will still return false because
getSmallConstantMaxTripCount will return 0 when SCEV predicates
are required. This patch changes getSmallConstantMaxTripCount to take
an optional Predicates pointer argument so that we can permit
functions such as isDereferenceableAndAlignedInLoop to consider more
cases.
Commit: 0b0a37e158bcf6d0667b4744b3d335f91578e0c9
https://github.com/llvm/llvm-project/commit/0b0a37e158bcf6d0667b4744b3d335f91578e0c9
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaStmt.cpp
M clang/test/SemaCXX/attr-musttail.cpp
Log Message:
-----------
[clang] Lifetime of locals must end before musttail call (#109255)
The lifetimes of local variables and function parameters must end before
the call to a [[clang::musttail]] function, instead of before the
return, because we will not have a stack frame to hold them when doing
the call.
This documents this limitation, and adds diagnostics to warn about some
code which is invalid because of it.
Commit: f28a0355364b9f09fa3d47720af4cf7431721de6
https://github.com/llvm/llvm-project/commit/f28a0355364b9f09fa3d47720af4cf7431721de6
Author: abhishek-kaushik22 <abhishek.kaushik at intel.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/LLVMTargetMachine.cpp
Log Message:
-----------
Fix memory leak in LLVMTargetMachine.cpp (#109610)
Because `MAB` is a raw pointer, it could potentially leak memory because
of the `||` in the null check.
Commit: 8632e8bd64d6f02e571777390274c262d5c85167
https://github.com/llvm/llvm-project/commit/8632e8bd64d6f02e571777390274c262d5c85167
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
A llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
Log Message:
-----------
AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)
Commit: cd80ed424b13790a65365a0145fa9b1b51b13680
https://github.com/llvm/llvm-project/commit/cd80ed424b13790a65365a0145fa9b1b51b13680
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
Log Message:
-----------
[llvm-exegesis] Fix -Wunused-variable in BenchmarkRunner.cpp (NFC)
/llvm-project/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp:415:18:
error: unused variable 'CurrentCPU' [-Werror,-Wunused-variable]
unsigned int CurrentCPU;
^
1 error generated.
Commit: 3e0a76b1fd10d2f5f36d34a91b525c1d29685185
https://github.com/llvm/llvm-project/commit/3e0a76b1fd10d2f5f36d34a91b525c1d29685185
Author: futog <54807384+futog at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
M llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
M llvm/test/CodeGen/Mips/llvm-ir/shl.ll
M llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
M llvm/test/CodeGen/PowerPC/pr59074.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/pr38539.ll
M llvm/test/CodeGen/X86/scheduler-backtracking.ll
M llvm/test/CodeGen/X86/shift-i128.ll
M llvm/test/CodeGen/X86/shift-i256.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
Log Message:
-----------
[Codegen][LegalizeIntegerTypes] Improve shift through stack (#96151)
Minor improvement on cc39c3b17fb2598e20ca0854f9fe6d69169d85c7.
Use an aligned stack slot to store the shifted value.
Use the native register width as shifting unit, so the load of the
shift result is aligned.
If the shift amount is a multiple of the native register width, there is
no need to do a follow-up shift after the load. I added new tests for
these cases.
Co-authored-by: Gergely Futo <gergely.futo at hightec-rt.com>
Commit: 2612316f72b92d7905717c358aeab8b8141738a1
https://github.com/llvm/llvm-project/commit/2612316f72b92d7905717c358aeab8b8141738a1
Author: Viktoriia Bakalova <115406782+VitaNuo at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libcxxabi/src/demangle/ItaniumDemangle.h
M libcxxabi/test/test_demangle.pass.cpp
M llvm/include/llvm/Demangle/ItaniumDemangle.h
Log Message:
-----------
[ItaniumDemangle] Add template name to the substitutions list during demangling (#108538)
When demangling a template template parameter (`method<bool,
Bar>(Bar<bool> b)`), the current demangler version first enters the
template argument (`bool`) into the substitutions list, then the whole
template specialization (`Bar<bool>`). The template name (`Bar`) never
becomes a substitution candidate on its own.
This is different when mangling. Mangling `method<bool, Bar>(Bar<bool>
b, Bar<int> i)` substitutes the `Bar` in the second parameter with the
substitution for `TemplateTemplateParmDecl`.
This leads to a discrepancy between mangler and demangler, see
https://github.com/llvm/llvm-project/issues/108009.
Commit: bad544461a72cdf0e8301b0e80eef4e6661eee2b
https://github.com/llvm/llvm-project/commit/bad544461a72cdf0e8301b0e80eef4e6661eee2b
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove an outdated comment
Commit: d36f66b42d7abec73bb5b953612eef26e6c12e0a
https://github.com/llvm/llvm-project/commit/d36f66b42d7abec73bb5b953612eef26e6c12e0a
Author: Michael Halkenhäuser <MichaelGerald.Halkenhauser at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M offload/include/OpenMP/OMPT/Callback.h
M offload/include/OpenMP/OMPT/Interface.h
M offload/plugins-nextgen/common/CMakeLists.txt
R offload/plugins-nextgen/common/OMPT/OmptCallback.cpp
M offload/src/OpenMP/OMPT/Callback.cpp
M offload/src/exports
Log Message:
-----------
[NFC][offload][OMPT] Cleanup of OMPT internals (#109005)
Removed `OmptCallbacks.cpp` since relevant contents were duplicated.
Because of the static linking there should be no change in
functionality.
Commit: 7a181980b900683fd3e1ac9601a627c758f19a61
https://github.com/llvm/llvm-project/commit/7a181980b900683fd3e1ac9601a627c758f19a61
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Log Message:
-----------
[InstCombine] Fix nits in new xor fold
Followup to https://github.com/llvm/llvm-project/pull/105992,
use the simplifyXorInst helper and use getWithInstruction
consistently.
Commit: a72d7eea5413444249670579fecea6823fb3c564
https://github.com/llvm/llvm-project/commit/a72d7eea5413444249670579fecea6823fb3c564
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/include/clang/Frontend/MultiplexConsumer.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/IncrementalExecutor.cpp
M clang/lib/Interpreter/IncrementalParser.cpp
M clang/lib/Interpreter/IncrementalParser.h
M clang/lib/Interpreter/Interpreter.cpp
A clang/lib/Interpreter/InterpreterValuePrinter.cpp
M clang/unittests/Interpreter/CodeCompletionTest.cpp
M clang/unittests/Interpreter/InterpreterExtensionsTest.cpp
Log Message:
-----------
[clang-repl] Simplify the value printing logic to enable out-of-process. (#107737)
This patch improves the design of the IncrementalParser and Interpreter
classes. Now the incremental parser is only responsible for building the
partial translation unit declaration and the AST, while the Interpreter
fills in the lower level llvm::Module and other JIT-related
infrastructure. Finally the Interpreter class now orchestrates the AST
and the LLVM IR with the IncrementalParser and IncrementalExecutor
classes.
The design improvement allows us to rework some of the logic that
extracts an interpreter value into the clang::Value object. The new
implementation simplifies use-cases which are used for out-of-process
execution by allowing interpreter to be inherited or customized with an
clang::ASTConsumer.
This change will enable completing the pretty printing work which is in
llvm/llvm-project#84769
Commit: 7e7009fc5725fc2a9157212834cc995c91969cf1
https://github.com/llvm/llvm-project/commit/7e7009fc5725fc2a9157212834cc995c91969cf1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Interpreter/BUILD.gn
Log Message:
-----------
[gn build] Port a72d7eea5413
Commit: 31ac3d092bd047ab2c0bdcb6d527736472b9d4a6
https://github.com/llvm/llvm-project/commit/31ac3d092bd047ab2c0bdcb6d527736472b9d4a6
Author: sinan <sinan.lin at linux.alibaba.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Rewrite/RewriteInstance.cpp
R bolt/test/AArch64/Inputs/iplt.ld
R bolt/test/AArch64/ifunc.c
A bolt/test/AArch64/ifunc.test
A bolt/test/Inputs/ifunc.c
A bolt/test/Inputs/iplt.ld
A bolt/test/X86/ifunc.test
Log Message:
-----------
[BOLT] Add .iplt support to x86 (#106513)
Add X86 support for parsing .iplt section and symbols.
Commit: 57f5d8f2fe9ed55a03ce451811940726d6908f2e
https://github.com/llvm/llvm-project/commit/57f5d8f2fe9ed55a03ce451811940726d6908f2e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Only store single vector per VPValue in VPTransformState. (NFC)
After 8ec406757cb92 (https://github.com/llvm/llvm-project/pull/95842),
VPTransformState only stores a single vector value per VPValue.
Simplify the code by replacing the SmallVector in PerPartOutput with a
single Value * and rename to VPV2Vector for clarity.
Also remove the redundant Part argument from various accessors.
Commit: cff753f8768ff3a7afbc27adaf318ebbf419dcfa
https://github.com/llvm/llvm-project/commit/cff753f8768ff3a7afbc27adaf318ebbf419dcfa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] SimplifyDemandedVectorEltsForTargetNode - simplify X86ISD::VBROADCAST of 0'th element handling. NFC.
Avoid duplicate TLO.CombineTo calls.
Commit: 85220a0c651e565ab576c5be17c1ec5c9eb2a350
https://github.com/llvm/llvm-project/commit/85220a0c651e565ab576c5be17c1ec5c9eb2a350
Author: Kelvin Lee <kiyolee at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
Log Message:
-----------
[lldb][FreeBSD] Fix a typo in NativeProcessFreeBSD::MonitorSIGTRAP() (#109643)
Apparently a typo is causing compile error, added by https://github.com/llvm/llvm-project/pull/108504.
Commit: 677177bb60dbe0d551251058c28466c5d74cebac
https://github.com/llvm/llvm-project/commit/677177bb60dbe0d551251058c28466c5d74cebac
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/Mips/Mips.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.h
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-mult.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-sdiv.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-srem.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-udiv.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-urem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
Log Message:
-----------
[Mips] Fix mfhi/mflo hazard miscompilation about div and mult (#91449)
Fix issue1: In mips1-4, require a minimum of 2 instructions between a
mflo/mfhi and the next mul/dmult/div/ddiv/divu/ddivu instruction.
Fix issue2: In mips1-4, should not put mflo into the delay slot for the
return.
Fix https://github.com/llvm/llvm-project/issues/81291
Commit: 26f272ebbdf8dc4a81f3f7d7c8ccf99fd9398bfb
https://github.com/llvm/llvm-project/commit/26f272ebbdf8dc4a81f3f7d7c8ccf99fd9398bfb
Author: Pawan Nirpal <pawannirpal at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
A llvm/test/CodeGen/X86/canonicalize-vars.ll
Log Message:
-----------
[X86][SelectionDAG] - Add support for llvm.canonicalize intrinsic (#106370)
Enable support for fcanonicalize intrinsic lowering.
Commit: c712ab829b2050e2ac1652e032fa0786a43a31c0
https://github.com/llvm/llvm-project/commit/c712ab829b2050e2ac1652e032fa0786a43a31c0
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/new-delete.cpp
A clang/test/AST/ByteCode/placement-new.cpp
Log Message:
-----------
[clang][bytecode] Implement placement-new (#107033)
If we have a placement-new destination already, use that instead of
allocating a new one.
Tests are partially based on
`test/SemaCXX/cxx2c-constexpr-placement-new.cpp`.
Commit: c35ea627df441a3650f986ca79954b4b9d16bf24
https://github.com/llvm/llvm-project/commit/c35ea627df441a3650f986ca79954b4b9d16bf24
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/if_target.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/if_target.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/if_target.test
M llvm/utils/update_test_checks.py
Log Message:
-----------
update_test_checks: recognize %if in RUN line (#108972)
Recognize %if for target-specific cases in RUN line and keep only tool
command with options
Commit: e0bd8d3485075d24ecff2b4f5d9e2117853bd08b
https://github.com/llvm/llvm-project/commit/e0bd8d3485075d24ecff2b4f5d9e2117853bd08b
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
M llvm/test/Transforms/SLPVectorizer/arith-div-undef.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-insert-mask-size.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
M llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/catchswitch.ll
M llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
Log Message:
-----------
[SLP] Better way to filter target-specific tests (#106720)
When only an exclusive target e.g AArch64 was enabled, these tests were
previously shown as UNSUPPORTED.
This change allows us to run tests for cases with only a build for one
target.
Commit: 7773dcd16389b07e055a10336c42e71ffd57ad3d
https://github.com/llvm/llvm-project/commit/7773dcd16389b07e055a10336c42e71ffd57ad3d
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
Log Message:
-----------
[X86][NFC] Change test name and add a new test (#109638)
Address post commit comments in #108754.
Commit: 785337e2d97a712612a5956657e8dbf1cd140e46
https://github.com/llvm/llvm-project/commit/785337e2d97a712612a5956657e8dbf1cd140e46
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/scalable-fp-ext-trunc-illegal-type.ll
Log Message:
-----------
[LV][AArch64] Don't query registers for illegal scalable vector elts (#109411)
When trying to maximize vector bandwidth we ask TTI for the number of
registers required for a given operation. If the type of that operation
happens to be something illegal for scalable vectors (e.g.
<vscale x 4 x fp128>) then we would see a crash.
Instead, just return a default value and let the cost model reject the
invalid operation later.
Commit: f4eeae1244c83486e38e4b73715fa688d34bc244
https://github.com/llvm/llvm-project/commit/f4eeae1244c83486e38e4b73715fa688d34bc244
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/simple_early_exit.ll
Log Message:
-----------
[LoopVectorize] Address comments on PR #107004 left post-commit (#109300)
* Rename Speculative -> Uncountable and update tests.
* Add comments explaining why it's safe to ignore the predicates when
building up a list of exiting blocks.
* Reshuffle some code to do (hopefully) cheaper checks first.
Commit: b0dc7b5b8617e188a926cbe06918fedab2fd5df9
https://github.com/llvm/llvm-project/commit/b0dc7b5b8617e188a926cbe06918fedab2fd5df9
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/xtn.ll
Log Message:
-----------
[AArch64][GlobalISel] Prefer to use Vector Truncate (#105692)
Tries to combine scalarised truncates into vector truncate operations
EXAMPLE:
`%a(i32), %b(i32) = G_UNMERGE %src(<2 x i32>)`
`%T_a(i16) = G_TRUNC %a(i32)`
`%T_b(i16) = G_TRUNC %b(i32)`
`%Imp(i16) = G_IMPLICIT_DEF(i16)`
`%dst(v8i16) = G_MERGE_VALUES %T_a(i16), %T_b(i16), %Imp(i16),
%Imp(i16)`
===>
`%Imp(<2 x i32>) = G_IMPLICIT_DEF(<2 x i32>)`
`%Mid(<4 x s16>) = G_CONCAT_VECTORS %src(<2 x i32>), %Imp(<2 x i32>)`
`%dst(<4 x s16>) = G_TRUNC %Mid(<4 x s16>)`
Commit: f8f41bf92c92ebc9b113a2a573d12880b86d5af3
https://github.com/llvm/llvm-project/commit/f8f41bf92c92ebc9b113a2a573d12880b86d5af3
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaCXX/attr-gsl-owner-pointer-std.cpp
Log Message:
-----------
[clang] Apply the [[gsl::Owner]] or [[gsl::Pointer]] attributes to the STL template specialization declarations. (#109653)
Fixes #109442
Commit: 6f194a6dea4b4067336431e699ea3588417d4b96
https://github.com/llvm/llvm-project/commit/6f194a6dea4b4067336431e699ea3588417d4b96
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
Log Message:
-----------
[SimplifyCFG] Avoid truncation in linear map overflow check
This is supposed to test multiplication of the linear multiplifier
with the largest value it can be multiplied with. However, if
we truncate TableSize-1 here, it might not actually be the largest
value. I think in practice this still works out, because in cases
where we'd truncate the value here we'd also fail the NonMonotonic
check. But to match the intent of the code, we should treat the
truncating case as overflowing.
Commit: 6d216fb7b8546c04223e56002152c556926d1a1d
https://github.com/llvm/llvm-project/commit/6d216fb7b8546c04223e56002152c556926d1a1d
Author: Kristof Beyls <kristof.beyls at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/unittests/Core/BinaryContext.cpp
Log Message:
-----------
[perf2bolt] Improve heuristic to map in-process addresses to specific… (#109397)
… segments in Elf binary.
The heuristic is improved by also taking into account that only
executable segments should contain instructions.
Fixes #109384.
Commit: 3e0d37fd79faeb60a47ed8aace1c594ff7f637f2
https://github.com/llvm/llvm-project/commit/3e0d37fd79faeb60a47ed8aace1c594ff7f637f2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/tools/llvm-reduce/TestRunner.cpp
M llvm/tools/llvm-reduce/TestRunner.h
Log Message:
-----------
llvm-reduce: Simplify argument setup for ExecuteAndWait
Only need to append the input file for each iteration.
Commit: cee65092c95a216e63d970b5da1495eb33dd506a
https://github.com/llvm/llvm-project/commit/cee65092c95a216e63d970b5da1495eb33dd506a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Log Message:
-----------
[ARM] Avoid repeated hash lookups (NFC) (#109602)
Commit: 9a3348856ced274b9c7136d6726a18ca8975dad1
https://github.com/llvm/llvm-project/commit/9a3348856ced274b9c7136d6726a18ca8975dad1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp
Log Message:
-----------
[DWARFLinker] Avoid repeated hash lookups (NFC) (#109604)
Commit: ff9f1a6ea2a0031387d23ce510d43edd81a18a1e
https://github.com/llvm/llvm-project/commit/ff9f1a6ea2a0031387d23ce510d43edd81a18a1e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/Frontend/Rewrite/RewriteObjC.cpp
Log Message:
-----------
[Rewrite] Avoid repeated hash lookups (NFC) (#109605)
Commit: d6a6e25c5158be8a1b820aedf067fce394f7a313
https://github.com/llvm/llvm-project/commit/d6a6e25c5158be8a1b820aedf067fce394f7a313
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[AST] Avoid repeated hash lookups (NFC) (#109603)
Commit: a4232dc676908548afa36d4f4ad740131ce385e2
https://github.com/llvm/llvm-project/commit/a4232dc676908548afa36d4f4ad740131ce385e2
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_posix.h
M compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Log Message:
-----------
[rtsan][tsan] Fix va_args handling in open functions (#108291)
Check oflag to see if it contains O_CREAT / O_TMPFILE before unpacking parameters to avoid UB
Commit: 21627236363d629f6a5b820f45a6071371e4b8db
https://github.com/llvm/llvm-project/commit/21627236363d629f6a5b820f45a6071371e4b8db
Author: Chao Chen <116223022+chencha3 at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
Log Message:
-----------
[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition. (#109144)
The PR makes the following refine changes to the XeGPU dialect.
1. Separated the old `TensorDescAttr` into two independent attributes: `BlockTensorDescAttr` and `ScatterTensorDescAttr`
2. Renamed the `MemoryScopeAttr` to `MemorySpaceAttr` and updated the enumeration value for shared memory following OpenCL standard.
3. Introduced `transpose` UnitAttr to `StoreScatterOp`and `LoadGatherOp`
4. Added memory space check for `CreateNdDesc` and `CreateDesc` op, as well as valid and invalid test cases for them.
Commit: 0b524efa953ce4a1f41ff6abaa8e3c5f757e40e2
https://github.com/llvm/llvm-project/commit/0b524efa953ce4a1f41ff6abaa8e3c5f757e40e2
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
M llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
Log Message:
-----------
[RISCV][TTI] Reduce cost of a <N x i1> build_vector pattern (#109449)
This is a follow up to 7f6bbb3. When lowering a <N x i1> build_vector,
we currently chose to extend to i8, perform the build_vector there, and
then truncate back in vector. Our costing on the other hand accounts for
it as if we performed a vector extend, an insert, and a vector extract
for every element. This significantly over estimates the cost.
Note that we can likely do better in our build_vector lowering here by
packing the bits in scalar, and doing a build_vector of the packed bits.
Regardless, our costing should match our lowering.
Commit: ecb98f9fed65801d9ad2c138da7194496e18aeec
https://github.com/llvm/llvm-project/commit/ecb98f9fed65801d9ad2c138da7194496e18aeec
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M llvm/include/llvm-c/Core.h
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M polly/lib/CodeGen/RuntimeDebugBuilder.cpp
Log Message:
-----------
[IRBuilder] Remove uses of CreateGlobalStringPtr() (NFC)
Since the migration to opaque pointers, CreateGlobalStringPtr()
is the same as CreateGlobalString(). Normalize to the latter.
Commit: 09e94d09fd0f6ca7daac86f2c019473e0bd2f54e
https://github.com/llvm/llvm-project/commit/09e94d09fd0f6ca7daac86f2c019473e0bd2f54e
Author: Chao Chen <116223022+chencha3 at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
Log Message:
-----------
Revert "[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition. " (#109666)
Reverts llvm/llvm-project#109144
Commit: bf791566e1585cac21bd89f7d1381272f2ad40c9
https://github.com/llvm/llvm-project/commit/bf791566e1585cac21bd89f7d1381272f2ad40c9
Author: Piotr Sobczak <piotr.sobczak at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
Log Message:
-----------
[AMDGPU] Add test for readfirstlane with i1 type (#109657)
Add test for readfirstlane with i1 type to demonstrate the lowering
works.
Also simplify existing tests a bit - the declarations are not strictly
needed anymore.
Commit: b189b89bdeb74a933016bef6d85ae42b0c62b40e
https://github.com/llvm/llvm-project/commit/b189b89bdeb74a933016bef6d85ae42b0c62b40e
Author: Volodymyr Vasylkun <vvmposeydon at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/phi-with-multiple-unsimplifiable-values.ll
Log Message:
-----------
[InstCombine] Relax the conditons of fold of `ucmp`/`scmp` into phi by allowing the phi node to use the result of `ucmp`/`scmp` more than once (#109593)
This extends the optimisation implemented in #107769 by relaxing the
condtions to make it happen. Now, the value produced by `ucmp`/`scmp`
doesn't need to be one-use, but only one-user, meaning it can be present
in a single phi node more than once.
Commit: 04d8e364bbf758b2ecbc06b782f1b5dd91bd16e6
https://github.com/llvm/llvm-project/commit/04d8e364bbf758b2ecbc06b782f1b5dd91bd16e6
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
Log Message:
-----------
[IRBuilder] Deprecate CreateGlobalStringPtr() (NFC)
In favor of CreateGlobalString(), which has the same behavior.
The distinction used to be meaningful prior to the introduction
of opaque pointers.
Commit: 40d6497a97a61ef5ea38e615cc324104cb34072a
https://github.com/llvm/llvm-project/commit/40d6497a97a61ef5ea38e615cc324104cb34072a
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
A llvm/test/Transforms/AggressiveInstCombine/inline-strcmp-debugloc.ll
Log Message:
-----------
[DebugInfo] Transfer strcmp DILocation to generated inline code (#108531)
When AggressiveInstCombine inlines a strcmp call, we currently copy the
strcmp's DILocation only to the br instruction that jumps to the inline
code. While this is roughly analogous to the original call, it leaves
the generated code without any source location, which is precarious for
a memory operation. This patch copies the strcmp call's DILocation to
all the generated code.
An alternative solution would be to generate a new DILocation with a
line 0 location and an inlinedAt pointing to the original call location,
but this would still give limited attribution to the generated code
without traversing the DIE, whereas the submitted solution allows
attribution with just the line table; even though it would be
technically more accurate, pragmatically I believe that copying the
call's location will be more useful for users.
Commit: d4798498c4a30efb03eebb56415a69fa60107414
https://github.com/llvm/llvm-project/commit/d4798498c4a30efb03eebb56415a69fa60107414
Author: Volodymyr Vasylkun <vvmposeydon at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/compare-3way.ll
M llvm/test/Transforms/InstCombine/scmp.ll
M llvm/test/Transforms/InstCombine/select-select.ll
M llvm/test/Transforms/InstCombine/sink_to_unreachable.ll
M llvm/test/Transforms/InstCombine/ucmp.ll
Log Message:
-----------
[InstCombine] Fold `(x == y) ? 0 : (x > y ? 1 : -1)` into `ucmp/scmp(x,y)` (#107314)
This also handles commuted cases of the same fold, with either the
condition or the true/false values of the inner select being swapped.
Commit: be0b1142df7733633354ef1f73d0379bcd2ccb54
https://github.com/llvm/llvm-project/commit/be0b1142df7733633354ef1f73d0379bcd2ccb54
Author: Arseniy Zaostrovnykh <necto.ne at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/test/Analysis/stack-addr-ps.cpp
Log Message:
-----------
[analyzer][StackAddrEscapeChecker] Fix assert failure for alloca regions (#109655)
Fixes #107852
Make it explicit that the checker skips `alloca` regions to avoid the
risk of producing false positives for code with advanced memory
management.
StackAddrEscapeChecker already used this strategy when it comes to
malloc'ed regions, so this change relaxes the assertion and explicitly
silents the issues related to memory regions generated with `alloca`.
Commit: 53abbced3032b555d43f5b91fafa741c8a11a050
https://github.com/llvm/llvm-project/commit/53abbced3032b555d43f5b91fafa741c8a11a050
Author: Paul T Robinson <paul.robinson at sony.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
A clang/test/CodeGenCXX/debug-info-line-if-2.cpp
Log Message:
-----------
[DebugInfo] Correct the line attribution for IF branches (#108300)
An 'if' statement introduces a scope, but in some cases the conditional
branch to the then/else blocks had a debug-info attribution that did not
include the scope. This led to some inefficiency in the DWARF line
table.
Commit: 606557ddd68bcb082fb82fd21b0afb260222ae14
https://github.com/llvm/llvm-project/commit/606557ddd68bcb082fb82fd21b0afb260222ae14
Author: Wael Yehia <wyehia at ca.ibm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M compiler-rt/test/profile/Posix/instrprof-dlopen-norpath.test
Log Message:
-----------
[PGO] use atomics for profile counters in instrprof-dlopen-norpath.test
When two threads dlopen a shared library, one instance of the library
is loaded. Hence, code inside the library needs to be thread safe,
so use atomic updates for profile counters.
Commit: 50a1ab12abbe948e6d3f8418f11bfa1951c8d19e
https://github.com/llvm/llvm-project/commit/50a1ab12abbe948e6d3f8418f11bfa1951c8d19e
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args.ll
Log Message:
-----------
[LAA] Don't assume libcalls with output/input pointers can be vectorized (#108980)
LoopAccessAnalysis currently does not check/track aliasing from the
output pointers, but assumes vectorizing library calls with a mapping is
safe.
This can result in incorrect codegen if something like the following is
vectorized:
```
for(int i=0; i<N; i++) {
// No aliasing between input and output pointers detected.
sincos(cos_out[0], sin_out+i, cos_out+i);
}
```
Where for VF >= 2 `cos_out[1]` to `cos_out[VF-1]` is the cosine of the
original value of `cos_out[0]` not the updated value.
Commit: d61b2590f8e360695a5298311855c8649337969f
https://github.com/llvm/llvm-project/commit/d61b2590f8e360695a5298311855c8649337969f
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/CMakeLists.txt
Log Message:
-----------
[Clang-BOLT] Drop CDSplit flag
Breaks AArch64 Clang-BOLT builds:
https://github.com/llvm/llvm-project/pull/109351#issuecomment-2368584365
Commit: cce1fa39eabfca4907ff8d616618683eec1a5486
https://github.com/llvm/llvm-project/commit/cce1fa39eabfca4907ff8d616618683eec1a5486
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
Log Message:
-----------
[RISCV] Add zvfbfmin arithmetic cost model test coverage. NFC
Commit: 2cd20c255684257b86940bdda6861897f0bf3c00
https://github.com/llvm/llvm-project/commit/2cd20c255684257b86940bdda6861897f0bf3c00
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
R llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning-execution-mode.s
R llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning.s
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
Log Message:
-----------
Revert "[llvm-exegesis] Add support for pinning benchmarking process to a CPU (#85168)"
This reverts commit 6fc2451167ec991361dd0568de9a9fa2926f8da8.
This broke some more buildbots.
Commit: ce9a2c652104197a051db3788f3ec503cab3a79b
https://github.com/llvm/llvm-project/commit/ce9a2c652104197a051db3788f3ec503cab3a79b
Author: MichelleCDjunaidi <michellechrisalyn at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
A clang-tools-extra/docs/clang-tidy/ExternalClang-TidyExamples.rst
M clang-tools-extra/docs/clang-tidy/index.rst
Log Message:
-----------
[clang-tidy][doc] Add external examples (#106675)
Clang has a page where they list out external examples:
https://clang.llvm.org/docs/ExternalClangExamples.html. This mimics this page by adding some useful links specific to clang-tidy.
Commit: caf0897c9c7f6f2a142af06bff8680a23d1d4bf5
https://github.com/llvm/llvm-project/commit/caf0897c9c7f6f2a142af06bff8680a23d1d4bf5
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
Log Message:
-----------
[SPIR-V] Fix deprecation warnings after #102608 (#109447)
Follow up to fix warnings in the SPIRV backend after 2f50b280dc8e
"[DebugInfo] Enable deprecation of iterator-insertion methods (#102608)"
Commit: 40d8888f13fb54b0fe840deef23054de6544c184
https://github.com/llvm/llvm-project/commit/40d8888f13fb54b0fe840deef23054de6544c184
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/Status.h
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Utility/Status.cpp
M lldb/unittests/Utility/StatusTest.cpp
Log Message:
-----------
[lldb] Change the implementation of Status to store an llvm::Error (NFC) (#106774)
(based on a conversation I had with @labath yesterday in
https://github.com/llvm/llvm-project/pull/106442)
Most APIs that currently vend a Status would be better served by
returning llvm::Expected<> instead. If possibles APIs should be
refactored to avoid Status. The only legitimate long-term uses of Status
are objects that need to store an error for a long time (which should be
questioned as a design decision, too).
This patch makes the transition to llvm::Error easier by making the
places that cannot switch to llvm::Error explicit: They are marked with
a call to Status::clone(). Every other API can and should be refactored
to use llvm::Expected. In the end Status should only be used in very few
places.
Whenever an unchecked Error is dropped by Status it logs this to the
verbose API channel.
Implementation notes:
This patch introduces two new kinds of error_category as well as new
llvm::Error types. Here is the mapping of lldb::ErrorType to
llvm::Errors:
```
(eErrorTypeInvalid)
eErrorTypeGeneric llvm::StringError
eErrorTypePOSIX llvm::ECError
eErrorTypeMachKernel MachKernelError
eErrorTypeExpression llvm::ErrorList<ExpressionError>
eErrorTypeWin32 Win32Error
```
Relanding with built-in cloning support for llvm::ECError, and support
for initializing a Windows error with a NO_ERROR error code.
Commit: 8a9f66ca3118245f1ece5ba7ae6312889222eff9
https://github.com/llvm/llvm-project/commit/8a9f66ca3118245f1ece5ba7ae6312889222eff9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
R llvm/test/MC/RISCV/machine-csr-names-invalid.s
Log Message:
-----------
[RISCV] Remove machine-csr-names-invalid.s. NFC (#109595)
This appears to be redundant with rv32-only-csr-names.s which tests the
same registers and many more.
Commit: 27b5dc422cd3dc15b3d4410ba910d4b12272384d
https://github.com/llvm/llvm-project/commit/27b5dc422cd3dc15b3d4410ba910d4b12272384d
Author: Sean Perry <perry at ca.ibm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/CodeGen/Generic/allow-check.ll
M llvm/test/lit.cfg.py
Log Message:
-----------
Add target-byteorder for cases where endian in target triple is what matters (#107915)
I came across the subtly when setting up lit for z/OS and running it on
a Linux on Power machine. Linux on Power is little endian. This was
resulting in all of these tests being run even though the target triple
was z/OS which is big endian. The lit should really be checking if the
target is little endian not the host. The previous way didn't handle
cross compilation while running lit.
Commit: 8e8a0724c28642f49aeb313110522521d8359037
https://github.com/llvm/llvm-project/commit/8e8a0724c28642f49aeb313110522521d8359037
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
Log Message:
-----------
[llvm-debuginfod-find] Remove old parameter comment (#109637)
This patch removes a comment in llvm-debuginfod-find containing all the
cl::opt entries, which are redundant after the conversion to using
optTable. These seem to have been introduced in #108082 along with a
conversion to optTable.
Commit: 78ae2de4c692bea03d03e4c149b350543d220490
https://github.com/llvm/llvm-project/commit/78ae2de4c692bea03d03e4c149b350543d220490
Author: gonzalobg <65027571+gonzalobg at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
A llvm/test/CodeGen/NVPTX/fence-sm-90.ll
M llvm/test/CodeGen/NVPTX/fence.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
A llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
Log Message:
-----------
[NVPTX] Load/Store/Fence syncscope support (#106101)
Adds "initial" support for `syncscope` to the NVPTX backend
`load`/`store`/`fence` instructions.
Atomic Read-Modify-Write operations intentionally not supported as part
of this initial PR.
Commit: 93baa018e09bb3d4d5f4da0232321aff204caaeb
https://github.com/llvm/llvm-project/commit/93baa018e09bb3d4d5f4da0232321aff204caaeb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Log Message:
-----------
[LegalizeVectorTypes] Preserve original MemoryOperand and MemVT when widening fixed vector load to vp_load. (#109473)
Previously we were building a new memoperand with the size of the widened VT. This was causing a failure in our downstream with non-power of 2 vectorization. Alias analysis allowed rescheduling a 3 element vector load past 2 out of 3 scalar stores that overwrite what it was supposed to read.
Alias analysis considers it undefined behavior to read more than the size of the underlying object. There is an exception if the underying objects is sufficiently aligned, but that doesn't apply in my failing case.
Commit: f7d088b6168608682975759bf27b7c2ad0ae7117
https://github.com/llvm/llvm-project/commit/f7d088b6168608682975759bf27b7c2ad0ae7117
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/test/Sema/riscv-asm.c
Log Message:
-----------
[RISCV] Implement validateGlobalRegisterVariable. (#109596)
Only allow GPR registers and verify the size is the same as XLen.
This fixes the crash seen in #109588 by making it a frontend error.
gcc does accept the code so we may need to consider if we can fix the
backend. Some other targets I tried appear to have similar issues so it
might not be straightforward to fix.
Commit: 19f04e908667aade0efe2de9ae705baaf68c0ce2
https://github.com/llvm/llvm-project/commit/19f04e908667aade0efe2de9ae705baaf68c0ce2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Log Message:
-----------
[AArch64] Use MCRegister in more places. NFC
Commit: 3336d73126ae7ebaadf7c3a4d85e373eaae8cda6
https://github.com/llvm/llvm-project/commit/3336d73126ae7ebaadf7c3a4d85e373eaae8cda6
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/ABI.h
M lldb/include/lldb/Target/RegisterContextUnwind.h
M lldb/include/lldb/Target/UnwindLLDB.h
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/ArmUnwindInfo.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/FuncUnwinders.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/ABI.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
M lldb/source/Target/UnwindLLDB.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
Log Message:
-----------
[lldb][NFC] New names for the two RegisterLocation classes (#109611)
lldb has two RegisterLocation classes that do slightly different things.
UnwindPlan::Row::RegisterLocation (new: AbstractRegisterLocation) has a
description of how to find a register's value or location, not specific
to a particular stopping point. It may say that at a given offset into a
function, the caller's register has been spilled to stack memory at CFA
minus an offset. Or it may say that the caller's register is at a DWARF
exprssion.
UnwindLLDB::RegisterLocation (new: ConcreteRegisterLocation) is a
specific address where the register is currently stored, or the register
it has been copied into, or its value at this point in the current
function execution.
When lldb stops in a function, it interprets the
AbstractRegisterLocation's instructions using the register context and
stack memory, to create the ConcreteRegisterLocation at this point in
time for this stack frame.
I'm not thrilled with AbstractRegisterLocation and
ConcreteRegisterLocation, but it's better than the same name and it will
be easier to update them if someone suggests a better pair.
Commit: 62f3eae466cc6af101a9bfa21e2af4ff5c95658d
https://github.com/llvm/llvm-project/commit/62f3eae466cc6af101a9bfa21e2af4ff5c95658d
Author: Lei Huang <lei at ca.ibm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
M clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
Log Message:
-----------
[PowerPC] Fix incorrect store alignment for __builtin_vsx_build_pair() (#108606)
Fixes #107229
Commit: df0864e761107b07e38f5503e0cbee0cebb4c5e8
https://github.com/llvm/llvm-project/commit/df0864e761107b07e38f5503e0cbee0cebb4c5e8
Author: Fangrui Song <i at maskray.me>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Move elf::symtab into Ctx
Remove the global variable `symtab` and add a member variable
(`std::unique_ptr<SymbolTable>`) to `Ctx` instead.
This is one step toward eliminating global states.
Pull Request: https://github.com/llvm/llvm-project/pull/109612
Commit: 127349fcba81646389e4b8202b35405a5fdbef47
https://github.com/llvm/llvm-project/commit/127349fcba81646389e4b8202b35405a5fdbef47
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/cmake/modules/CheckCompilerFeatures.cmake
A libc/cmake/modules/compiler_features/check_float16_conversion.cpp
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/ManipulationFunctions.h
A libc/src/__support/FPUtil/cast.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/except_value_utils.h
M libc/src/__support/FPUtil/generic/CMakeLists.txt
M libc/src/__support/FPUtil/generic/FMA.h
M libc/src/__support/FPUtil/generic/add_sub.h
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/ceilf16.cpp
M libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp2f16.cpp
M libc/src/math/generic/expf16.cpp
M libc/src/math/generic/expm1f16.cpp
M libc/src/math/generic/floorf16.cpp
M libc/src/math/generic/rintf16.cpp
M libc/src/math/generic/roundevenf16.cpp
M libc/src/math/generic/roundf16.cpp
M libc/src/math/generic/truncf16.cpp
M libc/test/src/math/smoke/AddTest.h
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/DivTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/ModfTest.h
M libc/test/src/math/smoke/MulTest.h
M libc/test/src/math/smoke/NextTowardTest.h
M libc/test/src/math/smoke/SqrtTest.h
M libc/test/src/math/smoke/SubTest.h
M libc/test/src/math/smoke/exp10f16_test.cpp
M libc/test/src/math/smoke/exp2f16_test.cpp
M libc/test/src/math/smoke/expf16_test.cpp
M libc/test/src/math/smoke/expm1f16_test.cpp
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
[libc][math] Add floating-point cast independent of compiler runtime (#105152)
Fixes build and tests with compiler-rt on x86.
Commit: 5927c6745c2a60c368d7bcb789a1f561d62fa039
https://github.com/llvm/llvm-project/commit/5927c6745c2a60c368d7bcb789a1f561d62fa039
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/test/MC/AMDGPU/gfx10_unsupported.s
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_unsupported.s
A llvm/test/MC/AMDGPU/gfx940_unsupported.s
Log Message:
-----------
[AMDGPU][MC] Instructions not to be supported in GFX940 (#109225)
Buffer_store_lds_dword, buffer_wbinvl1, and buffer_wbinvl1_vol are
obsolete in GFX940 and should not be supported.
Commit: 1693c6392299d1d4bea5b07094c1c562b7ee533f
https://github.com/llvm/llvm-project/commit/1693c6392299d1d4bea5b07094c1c562b7ee533f
Author: Xiaoyang Liu <siujoeng.lau at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libcxx/docs/Status/Cxx23Issues.csv
Log Message:
-----------
[libc++][NFC] mark LWG3723 as implemented (#109356)
This patch marks LWG3723 as implemented, with the implementation
completed in commit 87f3ff3 and released in `libc++` 17.0.
Closes #105104
Commit: 97b0d2076f53f669f27dc6d0539a3d01f28381e7
https://github.com/llvm/llvm-project/commit/97b0d2076f53f669f27dc6d0539a3d01f28381e7
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/Status.h
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Utility/Status.cpp
M lldb/unittests/Utility/StatusTest.cpp
Log Message:
-----------
Revert "[lldb] Change the implementation of Status to store an llvm::Error (NFC) (#106774)"
This reverts commit 40d8888f13fb54b0fe840deef23054de6544c184.
One last Windows failure remaining.
Commit: 1c47fa9b620d0abb280647b4f361ada43784d00e
https://github.com/llvm/llvm-project/commit/1c47fa9b620d0abb280647b4f361ada43784d00e
Author: Daniel Hernandez-Juarez <dhernandez0 at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
Log Message:
-----------
[mlir][AMDGPU] Add support for AMD f16 math library calls (#108809)
In this PR we add support for AMD f16 math library calls
(`__ocml_*_f16`)
CC: @krzysz00 @manupak
Commit: 3db0f8c895d4e814a18b754f9afbb1e03bd839a5
https://github.com/llvm/llvm-project/commit/3db0f8c895d4e814a18b754f9afbb1e03bd839a5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/reduced-value-vectorized-later.ll
Log Message:
-----------
[SLP]Update TrackedToOrig mappings after reduction vectorization
Need to update mappings in TrackedToOrig to correctly provide mapping
between updated reduced value after vectorization and its original
value, otherwise the compiler might miss this update and it may cause
compiler crash later, when it tries to find the original instruction
mapping for the updated value.
Fixes https://github.com/llvm/llvm-project/issues/109376
Commit: 6267f121f510859f8722c34a4a8c75e4d93b0300
https://github.com/llvm/llvm-project/commit/6267f121f510859f8722c34a4a8c75e4d93b0300
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/src/__support/FPUtil/dyadic_float.h
Log Message:
-----------
[libc] Fix missing LIBC_TYPES_HAS_FLOAT16 guard around DyadicFloat::generic_as() (#109697)
See Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/93/builds/6872.
Commit: d1edef56e87631ca8712afe01ac560710a2334f2
https://github.com/llvm/llvm-project/commit/d1edef56e87631ca8712afe01ac560710a2334f2
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/Type.h
A llvm/include/llvm/SandboxIR/Utils.h
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Functions to find vectorizor-relevant properties (#109221)
When vectorizing, the destination type and value of stores is more
relevant than the type of the instruction itself. Similarly for return
instructions. These functions provide a convenient way to do that
without special-casing them everywhere, and avoids the need for
friending any class that needs access to Value::LLVMTy to calculate it.
Open to better naming.
Commit: 8be6b108fbd35c6f50db488a0a5462eba6852cfd
https://github.com/llvm/llvm-project/commit/8be6b108fbd35c6f50db488a0a5462eba6852cfd
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsNVPTX.def
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
Log Message:
-----------
[NVPTX] Remove nvvm.bitcast.* intrinsics (#107936)
Remove the following intrinsics which correspond directly to a bitcast:
- llvm.nvvm.bitcast.f2i
- llvm.nvvm.bitcast.i2f
- llvm.nvvm.bitcast.d2ll
- llvm.nvvm.bitcast.ll2d
Commit: f76dae15862959deb62ec200e0958d532c908f30
https://github.com/llvm/llvm-project/commit/f76dae15862959deb62ec200e0958d532c908f30
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Only store single scalar array per VPValue in VPTransState (NFC)
After 8ec406757cb92 (https://github.com/llvm/llvm-project/pull/95842),
VPTransformState only stores a single scalar vector per VPValue.
Simplify the code by replacing the nested SmallVector in PerPartScalars with
a single SmallVector and rename to VPV2Scalars for clarity.
Commit: e093bb9e5a6884842402e2cca03f002b514e4411
https://github.com/llvm/llvm-project/commit/e093bb9e5a6884842402e2cca03f002b514e4411
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning-execution-mode.s
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning.s
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
Log Message:
-----------
Reland "[llvm-exegesis] Add support for pinning benchmarking process to a CPU (#85168)" (#109688)
This reverts commit 2cd20c255684257b86940bdda6861897f0bf3c00.
This relands commit 9886788a8a500a1b429a6db64397c849b112251c.
This was causing more buildbot failures due to getcpu not being
available with glibc <=2.29. This patch fixes that by directly making
the syscall, assuming the syscall number macro is available.
Commit: 416c3ce0138ff4039dab13ff634ee6392b9a3c7b
https://github.com/llvm/llvm-project/commit/416c3ce0138ff4039dab13ff634ee6392b9a3c7b
Author: vporpo <vporpodas at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantExpr (#109491)
This patch implements an empty sandboxir::ConstantExpr class, mirroring
llvm::ConstantExpr.
Commit: 6e6d5eae765939cc4074bdd606658e78c4a2a559
https://github.com/llvm/llvm-project/commit/6e6d5eae765939cc4074bdd606658e78c4a2a559
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
A lldb/test/API/macosx/expedited-thread-pcs/Makefile
A lldb/test/API/macosx/expedited-thread-pcs/TestExpeditedThreadPCs.py
A lldb/test/API/macosx/expedited-thread-pcs/foo.c
A lldb/test/API/macosx/expedited-thread-pcs/main.cpp
Log Message:
-----------
[lldb] Don't invalid register context after setting thread pc's (#109499)
Some gdb remote serial protocol stubs will send the thread IDs and PCs
for all threads in a process in the stop-reply packet. lldb often needs
to know the pc values for all threads while at a private stop, and that
results in <n-1> read-register packets for <n> threads, and can be a big
performance problem when this is a hot code path.
GDBRemoteRegisterContext tracks the StopID of when its values were set,
and when the thread's StopID has incremented, it marks all values it has
as Invalid, and knows to refetch them.
We have a code path that resulted in setting the PCs for all the
threads, and then `ProcessGDBRemote::CalculateThreadStopInfo` *forcing*
an invalidation of all the register contexts, forcing us to re-read the
pc values for all threads except the one that stopped.
There are times when it is valid to force an invalidation of the
regsiter cache - for instance, if the layout of the registers has
changed because the processor state is different, or we've sent a
write-all-registers packet to the inferior and we want to make sure we
stay in sync with the inferior. But there was no reason for this method
to be forcing the register context to be invalid.
I added a test when running on Darwin systems, where debugserver always
sends the thread IDs and PCs, which turns on packet logging. The test
runs against an inferior which has 4 threads; it steps over a dlopen()
call, steps in to a user function with debug info, steps-over and
steps-in across source lines with multiple function calls, and then
examines the packet log and flags it as an error if lldb asked for the
pc value of any thread at any point in the debug session.
For this program and the operations we're doing, with debugserver that
provides thread IDs and PCs, we should never ask for the value of a pc
register.
rdar://136247381
Commit: 2b892b05025b6e0ed2f211435f99838ea3bbccd8
https://github.com/llvm/llvm-project/commit/2b892b05025b6e0ed2f211435f99838ea3bbccd8
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/tools/UpdateTestChecks/lit.local.cfg
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-basic.test
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/lit.local.cfg
M llvm/utils/UpdateTestChecks/common.py
A llvm/utils/update_mc_test_checks.py
Log Message:
-----------
added a script to update llvm-mc test file (#107246)
Added a script to update the test file generated by llvm-mc binary. The
script accepts .s and .txt for asm and dasm.
For mc test I am targetting there is no function name which can be used
as a key, thus no clear mapping between input and output. The script
assumes the test are always line-by-line and it update the output marker
for each test line-by-line.
---------
Co-authored-by: Alexander Richardson <mail at alexrichardson.me>
Commit: 706e71076e0276747e7ae94e3f8a7f73a45e5b6e
https://github.com/llvm/llvm-project/commit/706e71076e0276747e7ae94e3f8a7f73a45e5b6e
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll
R llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll
R llvm/test/Transforms/SLPVectorizer/X86/external-user-instruction-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/extract-many-users-buildvector.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractelement-insertpoint.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/extracts-with-undefs.ll
R llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll
R llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-const-undef.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-postpone.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-uses-vectorized-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-multiuse-with-insertelement.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-user-not-min.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-node-vectorized-insts.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-uses-with-deps-in-first.ll
R llvm/test/Transforms/SLPVectorizer/X86/one-element-vector.ll
A llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
A llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
A llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
A llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
A llvm/test/Transforms/SLPVectorizer/extractlements-gathered-first-node.ll
A llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
A llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
A llvm/test/Transforms/SLPVectorizer/gep-with-extractelement-many-users.ll
A llvm/test/Transforms/SLPVectorizer/insert-crash-index.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-const-undef.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-multiple-uses.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
A llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-node-with-multi-users.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
A llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
A llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
A llvm/test/Transforms/SLPVectorizer/one-element-vector.ll
Log Message:
-----------
[SLP] Move some of X86 tests to common directory (#107587)
Some of the tests from the X86 directory can be generalized to improve
coverage for other architectures
Commit: 3138eb500c9462bcb6899088d49644adb4d90f62
https://github.com/llvm/llvm-project/commit/3138eb500c9462bcb6899088d49644adb4d90f62
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/CodeGenHwModes.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.h
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467)
Use const record pointers in TableGen/Common files.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
Commit: 74405b9d74d974523c0f9172a9b0c1cfd7320356
https://github.com/llvm/llvm-project/commit/74405b9d74d974523c0f9172a9b0c1cfd7320356
Author: vporpo <vporpodas at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement a few Instruction member functions (#109709)
This patch implements some of the missing member functions of
sandboxir::Instruction.
Commit: 954ab83e6a8acb7a78936cfa3e2284b1eaf8b722
https://github.com/llvm/llvm-project/commit/954ab83e6a8acb7a78936cfa3e2284b1eaf8b722
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/MC/AMDGPU/amdhsa-kd-kernarg-preload.s
Log Message:
-----------
[AMDGPU] Include unused preload kernarg in KD total SGPR count (#104743)
Unlike with implicitly preloaded data UserSGPRs firmware is unable to
handle cases where SGPRs for kernel arguments contain preloaded data but
not are not explicitly referenced in the kernel. We need to include
these preloaded SGPRs in the GRANULATED_WAVEFRONT_SGPR_COUNT calculation
to not clobber SGPRs in adjacent waves.
Commit: e44ecf76e049474190c33cd737642a0a066fb6b0
https://github.com/llvm/llvm-project/commit/e44ecf76e049474190c33cd737642a0a066fb6b0
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/test/CodeGen/X86/section-stats.ll
Log Message:
-----------
[llvm][ELF] Add ELF header/section header table size statistics (#109345)
Followup to #102363. This makes the `elf-object-writer.*Bytes` stats sum
up to `assembler.ObjectBytes`.
Commit: 16d11e26f36fa0de8ef6e402bb85e32bf7c7acd6
https://github.com/llvm/llvm-project/commit/16d11e26f36fa0de8ef6e402bb85e32bf7c7acd6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
M libc/docs/gpu/support.rst
M libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/newhdrgen/yaml/stdlib.yaml
M libc/spec/stdc.td
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/gpu/CMakeLists.txt
A libc/src/stdlib/gpu/system.cpp
A libc/src/stdlib/system.h
M libc/utils/gpu/server/rpc_server.cpp
Log Message:
-----------
[libc] Add GPU support for the 'system' function (#109687)
Summary:
This function can easily be implemented by forwarding it to the host
process. This shows up in a few places that we might want to test the
GPU so it should be provided. Also, I find the idea of the GPU
offloading work to the CPU via `system` very funny.
Commit: 3bbe0f90f33357c27e3195207fa35c0fb44e426c
https://github.com/llvm/llvm-project/commit/3bbe0f90f33357c27e3195207fa35c0fb44e426c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/config/gpu/headers.txt
M libc/docs/gpu/support.rst
Log Message:
-----------
[libc] Add 'strings.h' header on the GPU (#109661)
Summary:
These are GNU extensions but still show up, the entrypoints were enabled
but we weren't emitting the header so they couldn't be used.
Commit: 1fae1314f1ff58f3601640c0a2c48cee3a322e5d
https://github.com/llvm/llvm-project/commit/1fae1314f1ff58f3601640c0a2c48cee3a322e5d
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/Status.h
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Utility/Status.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestGDBRemotePlatformFile.py
M lldb/unittests/Utility/StatusTest.cpp
Log Message:
-----------
[lldb] Change the implementation of Status to store an llvm::Error (NFC) (#106774)
(based on a conversation I had with @labath yesterday in
https://github.com/llvm/llvm-project/pull/106442)
Most APIs that currently vend a Status would be better served by
returning llvm::Expected<> instead. If possibles APIs should be
refactored to avoid Status. The only legitimate long-term uses of Status
are objects that need to store an error for a long time (which should be
questioned as a design decision, too).
This patch makes the transition to llvm::Error easier by making the
places that cannot switch to llvm::Error explicit: They are marked with
a call to Status::clone(). Every other API can and should be refactored
to use llvm::Expected. In the end Status should only be used in very few
places.
Whenever an unchecked Error is dropped by Status it logs this to the
verbose API channel.
Implementation notes:
This patch introduces two new kinds of error_category as well as new
llvm::Error types. Here is the mapping of lldb::ErrorType to
llvm::Errors:
```
(eErrorTypeInvalid)
eErrorTypeGeneric llvm::StringError
eErrorTypePOSIX llvm::ECError
eErrorTypeMachKernel MachKernelError
eErrorTypeExpression llvm::ErrorList<ExpressionError>
eErrorTypeWin32 Win32Error
```
Relanding with built-in cloning support for llvm::ECError, and support
for initializing a Windows error with a NO_ERROR error code, and
modifying TestGDBRemotePlatformFile.py to support different renderings
of ENOSYS.
Commit: 9ac00b85e05d21be658d6aa0c91cbe05bb5dbde2
https://github.com/llvm/llvm-project/commit/9ac00b85e05d21be658d6aa0c91cbe05bb5dbde2
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
Log Message:
-----------
[NVPTX] deprecate nvvm.rotate.* intrinsics, cleanup funnel-shift handling (#107655)
This change deprecates the following intrinsics which can be trivially
converted to llvm funnel-shift intrinsics:
- @llvm.nvvm.rotate.b32
- @llvm.nvvm.rotate.right.b64
- @llvm.nvvm.rotate.b64
Commit: 0a5edb4de408ae0405f85c3e4c6da5233f185f63
https://github.com/llvm/llvm-project/commit/0a5edb4de408ae0405f85c3e4c6da5233f185f63
Author: Youngsuk Kim <youngsuk.kim at hpe.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryData.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Passes/RetpolineInsertion.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp
Log Message:
-----------
[bolt] Don't call llvm::raw_string_ostream::flush() (NFC)
Don't call raw_string_ostream::flush(), which is essentially a no-op.
As specified in the docs, raw_string_ostream is always unbuffered.
( 65b13610a5226b84889b923bae884ba395ad084d for further reference )
Commit: 783bac7ffb8f0d58d7381d90fcaa082eb0be1c1d
https://github.com/llvm/llvm-project/commit/783bac7ffb8f0d58d7381d90fcaa082eb0be1c1d
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
A llvm/test/Analysis/CtxProfAnalysis/handle-select.ll
Log Message:
-----------
[ctx_prof] Handle `select` and its `step` instrumentation (#109185)
The `step` instrumentation shouldn't be treated, during use, like an `increment`. The latter is treated as a BB ID. The step isn't that, it's more of a type of value profiling. We need to distinguish between the 2 when really looking for BB IDs (==increments), and handle appropriately `step`s. In particular, we need to know when to elide them because `select`s may get elided by function cloning, if the condition of the select is statically known.
Commit: c9e2c38f2c9784b668da875b7b94074a8bb416f7
https://github.com/llvm/llvm-project/commit/c9e2c38f2c9784b668da875b7b94074a8bb416f7
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC][hwasan] Convert ShadowMapping into class (#109616)
In the next patch we can switch to enum.
Commit: 300051159b5d8caef1e74193ebfb1ed1bce21c5e
https://github.com/llvm/llvm-project/commit/300051159b5d8caef1e74193ebfb1ed1bce21c5e
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M bolt/test/X86/log.test
M bolt/test/perf2bolt/perf_test.test
Log Message:
-----------
[BOLT][test] Update log.test and perf_test
Address noisy tests by:
- perf_test: bumping sampling frequency to maximum,
- log.test: matching Binary Function "main"
Commit: 8dbb739ffb0880e4f739992d07dc6ba6edca9509
https://github.com/llvm/llvm-project/commit/8dbb739ffb0880e4f739992d07dc6ba6edca9509
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC][hwasan] Use `enum class` in `ShadowMapping` (#109617)
Commit: 3734fa8c724ce2af2f69886ca97c05c6c3717c34
https://github.com/llvm/llvm-project/commit/3734fa8c724ce2af2f69886ca97c05c6c3717c34
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/DXILMetadataAnalysis.h
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Target/DirectX/CMakeLists.txt
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
R llvm/lib/Target/DirectX/DXILMetadata.cpp
R llvm/lib/Target/DirectX/DXILMetadata.h
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
A llvm/test/CodeGen/DirectX/Metadata/lib-entries.ll
A llvm/test/CodeGen/DirectX/Metadata/multiple-entries-cs-error.ll
A llvm/test/CodeGen/DirectX/Metadata/target-profile-error.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags2.ll
M llvm/test/CodeGen/DirectX/strip-call-attrs.ll
M llvm/test/CodeGen/DirectX/typed_ptr.ll
Log Message:
-----------
[DXIL] Consume Metadata Analysis information in passes (#108034)
- Changed `DXILTranslateMetadata::translateMetadata()` to consume DXIL
Metadata Analysis information. Subsumed into `DXILTranslateMetedata.cpp`
the functionality in `DXILMetadata.*` files - that are hence deleted.
- Changed `DXILPrepare` pass to consume DXIL Metadata Analysis
information.
- Renamed `ModuleMetadataInfo::ShaderStage` to
`ModuleMetadataInfo::ShaderProfile` to better convey what it represents.
- Updated `unknown` target shader stage specification in triples of a
couple of tests.
- Added new tests for additional verification of `DXILTranslateMetadata`
pass functionality.
Commit: 9d3a57633ebb8251d2575696dfe53c67d3a47d33
https://github.com/llvm/llvm-project/commit/9d3a57633ebb8251d2575696dfe53c67d3a47d33
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Log Message:
-----------
[RISCV] Add explicit XLenVT cast to vector load/store patterns.
This seems to be needed to get the patterns to import into GISel
properly.
Unfortunately, it also adds ~400 bytes to the SelectionDAG table.
I'm hoping if we remove i32 as a legal type for GPR registers, this
will go down.
Commit: eddbd4eb081fedddd4028244418f89e4bf5ffb09
https://github.com/llvm/llvm-project/commit/eddbd4eb081fedddd4028244418f89e4bf5ffb09
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[clang][NFC] add static for internal linkage function (#109436)
Detected by clang-tidy misc-use-internal-linkage
Commit: eca5949031c31fe5ff5ad7a5df07bbce13379108
https://github.com/llvm/llvm-project/commit/eca5949031c31fe5ff5ad7a5df07bbce13379108
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/SanitizerMetadata.cpp
Log Message:
-----------
[codegen][NFC] add static mark for internal usage variable and function (#109431)
Detect by clang-tidy misc-use-internal-linkage
Commit: 083f0fa454b618d722424a4a530b91de18a1b3c0
https://github.com/llvm/llvm-project/commit/083f0fa454b618d722424a4a530b91de18a1b3c0
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC][hwasan] Remove code duplication in ShadowMapping::init (#109618)
The goal to is to reorder this function to make
initialization in following order:
1. Defaults
2. Target specific overrides
3. Explicit copt<> overrides
Commit: 3bb92b530f27166b9037b63568534d248ff80150
https://github.com/llvm/llvm-project/commit/3bb92b530f27166b9037b63568534d248ff80150
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Region.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Region.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/RegionTest.cpp
Log Message:
-----------
[SandboxVec] Tag insts in a Region with metadata. (#109353)
For each region, we create a metadata node. Then when an instruction is
added to the Region, it gets tagged with the metadata node for that
region. In the following example, we have a Region that contains only
the `%t0` instruction.
```
define i8 @foo(i8 %v0, i8 %v1) {
%t0 = add i8 %v0, 1, !sbvec !0
%t1 = add i8 %t0, %v1
ret i8 %t1
}
!0 = distinct !{!"region"}
```
This commit also adds a function to create regions from metadata already
present in a Function.
This metadata can be used for debugging: if we dump IR before a Region
pass, the IR will contain enough info to re-create the Region and run
the pass by itself in a later invocation.
---------
Co-authored-by: Alina Sbirlea <alina.g.simion at gmail.com>
Commit: f77bbc0b34f98a6e866a72ccd8ff18bee9fa4dc8
https://github.com/llvm/llvm-project/commit/f77bbc0b34f98a6e866a72ccd8ff18bee9fa4dc8
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.h
Log Message:
-----------
[WebAssembly] Apply clang-tidy fixes on AsmParser/TypeCheck (NFC) (#109692)
Fixes are mostly one of these:
- `auto` -> `auto *` when the type is a pointer
- Function names start with a lowercase letter
- Variable names start with an uppercase letter
- No need to have an `else` after a `return`
Diff without whitespaces is easier to view.
Commit: 00629752e622814649e67d6e5ecb02bf131b537d
https://github.com/llvm/llvm-project/commit/00629752e622814649e67d6e5ecb02bf131b537d
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
Log Message:
-----------
[SLP][REVEC] Fix cost model for getGatherCost with FixedVectorType ScalarTy. (#109369)
Commit: 0673642cab6b6a9eec20d4ea4ee6bc46db47e04c
https://github.com/llvm/llvm-project/commit/0673642cab6b6a9eec20d4ea4ee6bc46db47e04c
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
Log Message:
-----------
[hwasan] Replace "-hwasan-with-ifunc" and "-hwasan-with-tls" options (#109619)
Relationship between "-hwasan-mapping-offset",
"-hwasan-with-ifunc", and "-hwasan-with-tls" can
be to hard to understand.
Now we will have "-hwasan-mapping-offset",
presense of which will imply fixed shadow.
If "-hwasan-mapping-offset-dynamic" will set one
of 3 available dynamic shadows.
As-is "-hwasan-mapping-offset" has precedence over
"-hwasan-mapping-offset-dynamic". In follow up
patches we need to use the one with last
occurrence.
Commit: af1cf699f0bf62e54288ac3a5ada6050a41a57a1
https://github.com/llvm/llvm-project/commit/af1cf699f0bf62e54288ac3a5ada6050a41a57a1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Move OrigIdx == 0 check to start of lowerEXTRACT_SUBVECTOR. NFC (#109731)
Allows us to remove a separate check of OrigIdx != 0 for the mask case.
Commit: fd11c81a80608ddd4b33b664e28b426229aabde1
https://github.com/llvm/llvm-project/commit/fd11c81a80608ddd4b33b664e28b426229aabde1
Author: A. Jiang <de34 at live.cn>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M libcxx/include/__memory/unique_temporary_buffer.h
Log Message:
-----------
[libc++] Add `_LIBCPP_NO_CFI` to `__allocate_unique_temporary_buffer` (#109682)
Follows up #100914. Addresses the issue revealed in
https://github.com/llvm/llvm-project/pull/100914#discussion_r1771647801.
Commit: 6bed79b3f00d3e2c273bc36ed350f802d76607b3
https://github.com/llvm/llvm-project/commit/6bed79b3f00d3e2c273bc36ed350f802d76607b3
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Support/raw_ostream.h
M llvm/unittests/Support/raw_ostream_test.cpp
Log Message:
-----------
[Support] Add scaling support in `indent` (#109478)
Scaled indent is useful when indentation is always in steps of a fixed
number (the Scale) and still allow using the +/- operators to adjust
indentation.
Commit: 86c640323286f4d692a634373c71536795cd7290
https://github.com/llvm/llvm-project/commit/86c640323286f4d692a634373c71536795cd7290
Author: c8ef <c8ef at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M compiler-rt/lib/nsan/nsan.cpp
M compiler-rt/lib/nsan/nsan_flags.inc
A compiler-rt/test/nsan/fcmp.cpp
Log Message:
-----------
[compiler-rt][nsan] Add check-cmp flag (#108707)
Add check-cmp flag.
Closes #108435.
Commit: 2028687ecad01ccc135cdc03eca933d7eec24df4
https://github.com/llvm/llvm-project/commit/2028687ecad01ccc135cdc03eca933d7eec24df4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp
Log Message:
-----------
[DWARFLinkerTypeUnit] Simplify code around try_emplace (NFC) (#109670)
Without this patch, we first default-construct a value with
try_emplace and then immediately override it with a new value.
This patch inserts the final value with try_emplace and simplies the
code around it.
Commit: 3cd3202b785654b8ac6d3bcf9ee18efcdd5171b0
https://github.com/llvm/llvm-project/commit/3cd3202b785654b8ac6d3bcf9ee18efcdd5171b0
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/include/clang/Frontend/ASTUnit.h
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/tools/c-index-test/core_main.cpp
M clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
Log Message:
-----------
[Frontend] Teach LoadFromASTFile to take FileName by StringRef (NFC) (#109583)
Without this patch, several callers of LoadFromASTFile construct an
instance of std::string to be passed as FileName, only to be converted
back to StringRef when LoadFromASTFile calls ReadAST.
This patch changes the type of FileName to StringRef and updates the
callers.
Commit: 23558afaf2f82f53ada3e9b6da3f11412dd02c8f
https://github.com/llvm/llvm-project/commit/23558afaf2f82f53ada3e9b6da3f11412dd02c8f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Hoist duplicate code in lowerINSERT_SUBVECTOR. NFC (#109733)
Commit: 64e7cb266e54e689791ad499965ddb0f8a1a2262
https://github.com/llvm/llvm-project/commit/64e7cb266e54e689791ad499965ddb0f8a1a2262
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/Frontend/Rewrite/RewriteObjC.cpp
Log Message:
-----------
[Rewrite] Use auto (NFC)
I'm planning to change the type of BlockByCopyDecls and
BlockByRefDecls to SetVector. Declaring these iterators with auto
makes it easier to migrate to the new type.
Commit: 9b5a3036adbd9eed0f377cdf06aa622b917a1699
https://github.com/llvm/llvm-project/commit/9b5a3036adbd9eed0f377cdf06aa622b917a1699
Author: David Pagan <dave.pagan at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[OpenMP][Docs] Update OpenMP supported features table (#109726)
OpenMP features table: updated scope directive status from 'worked on'
to 'done' in section OpenMP 5.1 Implementation Details.
Commit: 29168e80ba6fabb96c2b45d9deb1e908e02f8a53
https://github.com/llvm/llvm-project/commit/29168e80ba6fabb96c2b45d9deb1e908e02f8a53
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/Attributes.h
M llvm/lib/IR/Attributes.cpp
Log Message:
-----------
[IR][Attribute] Add missing `const` def on `addAllocSizeParamAttr()`; NFC
Commit: f5eaadc38b8bbe547a5019b7ceb961978f36abde
https://github.com/llvm/llvm-project/commit/f5eaadc38b8bbe547a5019b7ceb961978f36abde
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Support/ModRef.cpp
M llvm/lib/Support/OptionStrCmp.cpp
Log Message:
-----------
[NFC] Fix line endings for ModRef.cpp/OptionStrCmp.cpp (#109712)
Commit: 0206181ada4b39f0324dfe977442c65c1693f0b1
https://github.com/llvm/llvm-project/commit/0206181ada4b39f0324dfe977442c65c1693f0b1
Author: Fangrui Song <i at maskray.me>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
Log Message:
-----------
[ELF] Pass Ctx & to Driver and Writer
Commit: b30b9eb7a8823c1b3bbcd1bf9452e743a17d9223
https://github.com/llvm/llvm-project/commit/b30b9eb7a8823c1b3bbcd1bf9452e743a17d9223
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/LiveInterval.h
M llvm/lib/CodeGen/LiveInterval.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
Log Message:
-----------
LiveInterval: Make verify functions return bool (#109672)
This will allow the MachineVerifier to check these properties
instead of just asserting
Commit: fa089b014b41db4ef90378c7eae35306402cfcb3
https://github.com/llvm/llvm-project/commit/fa089b014b41db4ef90378c7eae35306402cfcb3
Author: SJW <48454132+sjw36 at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
M mlir/test/Dialect/SCF/loop-pipelining.mlir
Log Message:
-----------
[SCF] Fixed epilogue predicates in loop pipelining (#108964)
The computed loop iteration is zero based, so only check it is less than
zero. This fixes the case when lower bound is not zero.
Commit: cde7b30268a85a3e7900a31534a97e7eb4de9236
https://github.com/llvm/llvm-project/commit/cde7b30268a85a3e7900a31534a97e7eb4de9236
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
AMDGPU: Fix missing functions in MIR tests
This function was in the IR section, but not present in the MIR
function list.
Commit: 63b2595846b86b4e4eb9afba5e97dd64e8135c10
https://github.com/llvm/llvm-project/commit/63b2595846b86b4e4eb9afba5e97dd64e8135c10
Author: sstipano <146831748+sstipano at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
A llvm/test/CodeGen/AMDGPU/freeze.ll
Log Message:
-----------
[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)
G_FREEZE was legal for <13 x S32> which caused an infinite loop in the
combiner
Commit: 2c58063435ce4717a949585bc5c32ecf98a77238
https://github.com/llvm/llvm-project/commit/2c58063435ce4717a949585bc5c32ecf98a77238
Author: Sergey Kozub <skozub at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/include/mlir-c/BuiltinTypes.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Types.h
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Types.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/python/mlir/extras/types.py
M mlir/test/IR/attribute.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/python/ir/builtin_types.py
M mlir/utils/lldb-scripts/mlirDataFormatters.py
M mlir/utils/tree-sitter-mlir/grammar.js
Log Message:
-----------
[MLIR] Add f4E2M1FN type (#108877)
This PR adds `f4E2M1FN` type to mlir.
`f4E2M1FN` type is proposed in [OpenCompute MX
Specification](https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf).
It defines a 4-bit floating point number with bit layout S1E2M1. Unlike
IEEE-754 types, there are no infinity or NaN values.
```c
f4E2M1FN
- Exponent bias: 1
- Maximum stored exponent value: 3 (binary 11)
- Maximum unbiased exponent value: 3 - 1 = 2
- Minimum stored exponent value: 1 (binary 01)
- Minimum unbiased exponent value: 1 − 1 = 0
- Has Positive and Negative zero
- Doesn't have infinity
- Doesn't have NaNs
Additional details:
- Zeros (+/-): S.00.0
- Max normal number: S.11.1 = ±2^(2) x (1 + 0.5) = ±6.0
- Min normal number: S.01.0 = ±2^(0) = ±1.0
- Min subnormal number: S.00.1 = ±2^(0) x 0.5 = ±0.5
```
Related PRs:
- [PR-95392](https://github.com/llvm/llvm-project/pull/95392) [APFloat]
Add APFloat support for FP4 data type
- [PR-105573](https://github.com/llvm/llvm-project/pull/105573) [MLIR]
Add f6E3M2FN type - was used as a template for this PR
- [PR-107999](https://github.com/llvm/llvm-project/pull/107999) [MLIR]
Add f6E2M3FN type
Commit: f6a8eb98b13ee50c67ecf4804461a23fba7398aa
https://github.com/llvm/llvm-project/commit/f6a8eb98b13ee50c67ecf4804461a23fba7398aa
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/MC/AMDGPU/flat-global.s
A llvm/test/MC/AMDGPU/gfx10_flat_instructions_err.s
A llvm/test/MC/AMDGPU/gfx11_flat_instructions_err.s
A llvm/test/MC/AMDGPU/gfx12_flat_instructions_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt
Log Message:
-----------
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
Some flat instructions have an saddr operand. When 'null' is provided as
saddr, it may have the same encoding as another instruction. For
example, the instructions 'global_atomic_add v1, v2, null' and
'global_atomic_add v[1:2], v2, off' have the same encoding. This patch
disallows having null as saddr.
Commit: 78ff736db2313642c3d8dd74beee3bc0b21c5c2a
https://github.com/llvm/llvm-project/commit/78ff736db2313642c3d8dd74beee3bc0b21c5c2a
Author: David Green <david.green at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
Log Message:
-----------
[ARM] Fix VMOVRRD combine with non-canonical inserts. (#109639)
In some situations, in the test case here with the multiple calls being
late legalized, we can see inserts of the form:
```
b = insert a, x, 0
c = insert b, y, 1
d = insert c, z, 0
bc = bitcast d
e = extract bc, 0
r = vmovrrd e
```
The redundant insert will usually be removed, but in some cases are not
prior to PerformVMOVRRDCombine. The code was finding the first insert
from each lane (x and y), as opposed to the last (z and y).
Commit: 5ca09d617da89c4466347030e2949dc5713eabcb
https://github.com/llvm/llvm-project/commit/5ca09d617da89c4466347030e2949dc5713eabcb
Author: David Green <david.green at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/test/CodeGen/ARM/expand-pseudos.mir
M llvm/test/CodeGen/ARM/vbsl.ll
Log Message:
-----------
[ARM] Fix VBSL Pseudo kill flags. (#109629)
When expanding a VBSP pseudo into VMOV; VBSL, if the first reg was
killed in the BSP then the kill flags could be incorrect copied to the
mov (vorr) and the vbsl. Drop the kill flags.
Note that this sometimes comes up when all the operands of the VBSP are
the same, which can be optimized separately.
Commit: 1493c247b687160aa92cf13ac1c6f363870bbac0
https://github.com/llvm/llvm-project/commit/1493c247b687160aa92cf13ac1c6f363870bbac0
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
Log Message:
-----------
[ASan][test] Fix TestCases/Posix/stack-overflow.cpp on Solaris/sparcv9 (#109101)
When ASan testing is enabled on SPARC as per PR #107405, the
```
AddressSanitizer-sparc-sunos :: TestCases/Posix/stack-overflow.cpp
```
test `FAIL`s:
```
compiler-rt/test/asan/TestCases/Posix/stack-overflow.cpp:80:12: error: CHECK: expected string not found in input
// CHECK: {{stack-overflow on address 0x.* \(pc 0x.* bp 0x.* sp 0x.* T.*\)}}
^
AddressSanitizer:DEADLYSIGNAL
AddressSanitizer:DEADLYSIGNAL
=================================================================
==11358==ERROR: AddressSanitizer: SEGV on unknown address 0xff3fff90 (pc 0x000db0c0 bp 0xfeed59f8 sp 0xfeed5978 T0)
==11358==The signal is caused by a READ memory access.
AddressSanitizer:DEADLYSIGNAL
AddressSanitizer: nested bug in the same thread, aborting.
```
It turns out that `sanitizer_linux.cpp` (`GetPcSpBp`) tries to
dereference the stack pointer to get at the saved frame pointer, which
cannot work since `sp` has been invalidated by the stack overflow in the
test. The access attempt thus leads to a second `SEGV`.
Solaris `walkcontext(3C)` doesn't have that problem: in the original
OpenSolaris sources (`$SRC/lib/libc/port/gen/walkstack.c`) they used
`/proc/self/as` to avoid the fault, which is quite heavy-handed. Solaris
11.4 uses a non-faulting load instead (`load_no_fault_uint32`, which
just uses the `lduwa` insn).
This patch follows this lead, returning a `NULL` `bp` in the failure
case. Unfortunately, this leads to `SEGV`s in the depth of the unwinder,
so this patch avoids printing a stack trace in this case.
Tested on `sparcv9-sun-solaris2.11` and `sparc64-unknown-linux-gnu`.
Commit: 4ac141683c310447f0efba775dc59b2145511ac0
https://github.com/llvm/llvm-project/commit/4ac141683c310447f0efba775dc59b2145511ac0
Author: tomasz-kaminski-sonarsource <79814193+tomasz-kaminski-sonarsource at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/CXX/class/class.friend/p7-cxx20.cpp
M clang/test/CXX/class/class.mfct/p1-cxx20.cpp
Log Message:
-----------
[C++20][Modules] NFC Reworked handling of inline for functions defined in class (#109470)
Reworked handling of implicit inline marking for member and friend
function defined in class.
Now, we handle it in an additive manner, i.e. if such in-class functions
are inline implicitly by language rules,
we mark the as `setImplicitInline`, and perform no action otherwise.
As we never remove inline specifier, the implementation is orthogonal to
other sources of inline
(like `inline`, `constexpr`, e.t.c), and we do not need to handle them
specially.
Also included test for `constexpr`, `consteval` and global module cases.
Commit: 3907d186d627f8957627b2861cf6f879d07c93c2
https://github.com/llvm/llvm-project/commit/3907d186d627f8957627b2861cf6f879d07c93c2
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Log Message:
-----------
[sanitizer_common] Heed __ndbl_ prefix for 32-bit Linux/sparc64 inter… (#109106)
…ceptors
When ASan testing is enabled on SPARC as per PR #107405, a couple of
tests `FAIL` on Linux/sparc64:
```
AddressSanitizer-sparc-linux :: TestCases/printf-2.c
AddressSanitizer-sparc-linux :: TestCases/printf-3.c
AddressSanitizer-sparc-linux :: TestCases/printf-4.c
AddressSanitizer-sparc-linux :: TestCases/printf-5.c
SanitizerCommon-asan-sparc-Linux :: Linux/unexpected_format_specifier_test.cpp
```
It turns out the interceptors aren't used since on Linux/sparc64
`double` and `long double` are the same, and a couple of `stdio`
functions are prefixed with `__nldbl_` (no long double) accordingly.
This patch handles this.
Tested on `sparc64-unknown-linux-gnu`.
Commit: 4a264c559922a8754a0e28fbf316ba667ec19798
https://github.com/llvm/llvm-project/commit/4a264c559922a8754a0e28fbf316ba667ec19798
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
Log Message:
-----------
[sanitizer_common] Fix GetArgsAndEnv on Linux/sparc64 (#109109)
When ASan testing is enabled on SPARC as per PR #107405, the
```
AddressSanitizer-sparc-linux :: TestCases/Posix/print_cmdline.cpp
```
test `FAIL`s. Either `ASAN_OPTIONS=print_cmdline=true` yielded binary
garbage in the `Command:` output or just an empty string.
It turns out one needs to apply an offset to `__libc_stack_end` to get
at the actual `argc`/`argv`, as described in `glibc`'s
`sysdeps/sparc/sparc{32,64}/dl-machine.h` (`DL_STACK_END`).
This patch does this, fixing the test.
Tested on `sparc64-unknown-linux-gnu`.
Commit: d814006c0aedf806f2ea09660c26f51099020b2c
https://github.com/llvm/llvm-project/commit/d814006c0aedf806f2ea09660c26f51099020b2c
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/test/asan/TestCases/Posix/coverage-fork.cpp
Log Message:
-----------
[ASan][test] Fix Posix/coverage-fork.cpp on Solaris (#109626)
With ASan testing enabled on SPARC as per PR #107405, the
```
AddressSanitizer-sparc-sunos-dynamic :: TestCases/Posix/coverage-fork.cpp
```
test occasionally `FAIL`s on Solaris/sparcv9:
```
compiler-rt/test/asan/TestCases/Posix/coverage-fork.cpp:46:15: error: CHECK-DAG: expected string not found in input
// CHECK-DAG: Parent PID: [[ParentPID:[0-9]+]]
^
```
It turns out that the output for parent and child processes is
interleaved like
```
Parent PID: Child PID: 27426
27425
```
Checking with `truss` shows that the `fprintf`s are implemented as 3
separate `write`s:
```
28489: write(2, " P a r e n t P I D : ", 12) = 12
28489: write(2, " 2 8 4 8 9", 5) = 5
28489: write(2, "\n", 1) = 1
```
To avoid this, this patch switches the test to use `snprintf`/`write` to
guarantee the output is atomic.
Tested on `sparcv9-sun-solaris2.11`, `amd64-pc-solaris2.11`, and
`x86_64-pc-linux-gnu`.
Commit: debc325bb1f58025c44393408a2b5a53ef8041f9
https://github.com/llvm/llvm-project/commit/debc325bb1f58025c44393408a2b5a53ef8041f9
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
Log Message:
-----------
[MIPS] Fix failing to legalize load+call with vector of non-p2 integer (#109625)
Add a condition to check whether the vector element type is a power of 2.
Fixes #102870.
Commit: 5cd0900ef6eb97d72803bdca7180538a40431722
https://github.com/llvm/llvm-project/commit/5cd0900ef6eb97d72803bdca7180538a40431722
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
A llvm/test/Transforms/InstCombine/icmp-inttoptr.ll
Log Message:
-----------
[InstCombine] Compare `icmp inttoptr, inttoptr` values directly (#107012)
InstCombine already has some rules for `icmp ptrtoint, ptrtoint` to drop
the casts and compare the source values. This change adds the same for
the reverse case with `inttoptr`.
Commit: 3dbd929ea6af134650dd1d91baeb61a4fc1b0eb8
https://github.com/llvm/llvm-project/commit/3dbd929ea6af134650dd1d91baeb61a4fc1b0eb8
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Log Message:
-----------
[AMDGPU][NFC] Update comment referring to SIRemoveShortExecBranches pass (#109756)
That pass no longer exists, since
5df2af8b0ef33f48b1ee72bcd27bc609b898da52 has merged it into
SIPreEmitPeephole.
Commit: e4d34261f85050af340ade9a7dcd332f11b4485f
https://github.com/llvm/llvm-project/commit/e4d34261f85050af340ade9a7dcd332f11b4485f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/codegen.m
Log Message:
-----------
[clang][bytecode] Ignore CPointerToObjCPointerCasts (#109760)
Commit: 14ab6190f6d1813cc5774dec2623862e1bd6876f
https://github.com/llvm/llvm-project/commit/14ab6190f6d1813cc5774dec2623862e1bd6876f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
M llvm/test/CodeGen/X86/canonicalize-vars.ll
Log Message:
-----------
[X86] Cleanup check prefixes in FCANONICALIZE tests for better sharing
Commit: 4b964002403a9b9be934174391ff5b698691a26b
https://github.com/llvm/llvm-project/commit/4b964002403a9b9be934174391ff5b698691a26b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/AST/ByteCode/placement-new.cpp
Log Message:
-----------
[clang][bytecode] Allow placement-new in std functions pre-C++26 (#109753)
Commit: b75174d05aa033a382d4c088e96e068a774f46da
https://github.com/llvm/llvm-project/commit/b75174d05aa033a382d4c088e96e068a774f46da
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
M compiler-rt/test/sanitizer_common/TestCases/Linux/prctl.cpp
Log Message:
-----------
[compiler-rt] prctl interception update, SECCOMP_MODE_FILTER support. (#107722)
Commit: eabc8857e77c94a09624c12cc690753f68b87825
https://github.com/llvm/llvm-project/commit/eabc8857e77c94a09624c12cc690753f68b87825
Author: eddyz87 <eddyz87 at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/BPF.cpp
M clang/test/Preprocessor/bpf-predefined-macros.c
Log Message:
-----------
[BPF] make __BPF_FEATURE_MAY_GOTO available for cpuv1 (#108071)
For some reason `__BPF_FEATURE_MAY_GOTO` is available for CPUs v{2,3,4}
but is not available for CPU v1. This limitation is arbitrary:
- the instruction is never produced by LLVM backend;
- on Linux Kernel side this instruction is available in kernels that
also support CPUv4.
Hence, it is more consistent to either always allow
`__BPF_FEATURE_MAY_GOTO` or only allow it for CPUv4.
Commit: 70529b24a30943d46e361d2990268499921e28a2
https://github.com/llvm/llvm-project/commit/70529b24a30943d46e361d2990268499921e28a2
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/test/MC/Disassembler/X86/apx/kmov.txt
Log Message:
-----------
[X86][APX] Do not emit {evex} prefix for memory variant (#109759)
This was mistakely changed by #109579, which doesn't match with other
EVEX decoding.
Commit: c5672e21ca2a16ff18cdaa83db11d2edb84c5e14
https://github.com/llvm/llvm-project/commit/c5672e21ca2a16ff18cdaa83db11d2edb84c5e14
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
Log Message:
-----------
[AArch64][CostModel] Reduce the cost of fadd reduction with fast flag (#108791)
fadd reduction with
1. Fast flag set
2. No of elements in input vector is power of 2 results in series of
faddp instructions. faddp instruction has latency/throughput identical
to fadd instruction and hence, we set relative cost=1 for faddp as well.
The change didn't show any regression with SPEC17-FP(C/C++),
llvm-test-suite on Neoverse-V2.
Commit: 3659aa8079e00d7bd4f2d9c68c404a93ec297200
https://github.com/llvm/llvm-project/commit/3659aa8079e00d7bd4f2d9c68c404a93ec297200
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
A llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
A llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
Log Message:
-----------
[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
Both SGPR->VGPR and VGPR->AGPR spilling code give a fixup to the spill
frame indices referred in debug instructions so that they can be
entirely removed. The stack argument is present at 0th index in
DBG_VALUE and at 2nd index for DBG_VALUE_LIST.
Fixes: SWDEV-484156
Commit: 30dbbdd2ea25e3ab5596e1fb0474696b242a760c
https://github.com/llvm/llvm-project/commit/30dbbdd2ea25e3ab5596e1fb0474696b242a760c
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
Log Message:
-----------
[Bazel] Fix for 127349fcba81646389e4b8202b35405a5fdbef47
Commit: cc7b24a4d125e9a81480aaaa961a2b963bbb2ea2
https://github.com/llvm/llvm-project/commit/cc7b24a4d125e9a81480aaaa961a2b963bbb2ea2
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[NFC] Fix typos in comments (#109765)
Commit: bfd8f7ee4a85ae8873db14fa6e7e31223a1df169
https://github.com/llvm/llvm-project/commit/bfd8f7ee4a85ae8873db14fa6e7e31223a1df169
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/extractelement-fp.ll
Log Message:
-----------
[X86] SimplifyDemandedVectorEltsForTargetNode - reduce vector width of FRSQRT/FRCP ymm nodes.
If we only demand the lower subvector of a FRSQRT/FRCP node, then reduce the width of the instruction.
Commit: 396f6775143ffa80b9f0e72e7250613092d88124
https://github.com/llvm/llvm-project/commit/396f6775143ffa80b9f0e72e7250613092d88124
Author: Scott Egerton <9487234+ScottEgerton at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
R llvm/lib/Target/AMDGPU/AMDGPUInsertSingleUseVDST.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
R llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
R llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[AMDGPU] Remove unused VGPRSingleUseHintInsts feature (#109769)
Commit: fc661df41a206779a9323fb9dd49038c44084d5e
https://github.com/llvm/llvm-project/commit/fc661df41a206779a9323fb9dd49038c44084d5e
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lld/COFF/Writer.cpp
Log Message:
-----------
[LLD][COFF][NFC] Use dyn_cast on section chunks (#109701)
Instead of dyn_cast_or_null, chunk pointers are never null.
Commit: f664d313cd63893d7a4a496fdf0de988323b6b09
https://github.com/llvm/llvm-project/commit/f664d313cd63893d7a4a496fdf0de988323b6b09
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/fca2memcpy.ll
Log Message:
-----------
MemCpyOpt: replace an AA query with MSSA query (NFC) (#108535)
Fix a long-standing TODO.
Commit: 040bb37195d93f75cc7ce6b83254ab5db959a085
https://github.com/llvm/llvm-project/commit/040bb37195d93f75cc7ce6b83254ab5db959a085
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/float-induction.ll
Log Message:
-----------
[VPlan] Fix incorrect argument for CreateBinOp after 06c3a7d2d764.
06c3a7d2d764 incorrectly updated CreateBinOp to pass the debug location,
which gets interpreted as FPMath node. Remove the argument.
Commit: a3cf01d58587d81b184d40091a86d6b8bf92d240
https://github.com/llvm/llvm-project/commit/a3cf01d58587d81b184d40091a86d6b8bf92d240
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/docs/index.rst
A lldb/docs/resources/addinglanguagesupport.md
Log Message:
-----------
[lldb][docs] Resurrect the information on adding a new language (#109427)
This got deleted in e078c9507c3abb4d9bb2265c366b26557880a3e3, I presume
accidentally, because it didn't have a corresponding rst file for it.
So I've brought it back and converted it into Markdown. The content
remains accurate, from what I know at least.
It's a bit "now draw the rest of the owl" but if nothing else, it gives
you a bunch of important classes to go and research as a starting point.
You can see the original content here:
https://github.com/llvm/llvm-project/blob/5d71fc5d7b5ffe2323418a09db6eddaf84d6c662/lldb/www/adding-language-support.html
Commit: d4f38f43f5402041dd36977baa459830011d6ac6
https://github.com/llvm/llvm-project/commit/d4f38f43f5402041dd36977baa459830011d6ac6
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/test/CodeGen/ARM/preferred-function-alignment.ll
Log Message:
-----------
[LLVM][ARM][CodeGen]Define branch instruction alignment for m85 and m7 (#109647)
Branch instruction alignments were not defined for cortex-m85 and
cortex-m7 which misses an optimisation opportunity. With this patch we
see performance improvements as high as 5% on some benchmarks with most
around 1%.
Commit: ea902d1b36e4e3a7d7bdd0f7bce3c460b6dd6e80
https://github.com/llvm/llvm-project/commit/ea902d1b36e4e3a7d7bdd0f7bce3c460b6dd6e80
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/IR/Type.h
M llvm/lib/IR/LLVMContext.cpp
Log Message:
-----------
[IR] Remove deprecated opaque pointer migration methods
Remove the following methods:
* Type::getNonOpaquePointerElementType()
* Type::isOpaquePointerTy()
* LLVMContext::supportsTypedPointers()
* LLVMContext::setOpaquePointers()
These were used temporarily during the opaque pointers migration,
and are no longer needed.
Commit: 3d34053af61ff45e05d230d2678eb8e95322eb14
https://github.com/llvm/llvm-project/commit/3d34053af61ff45e05d230d2678eb8e95322eb14
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/test/Driver/relax.s
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/test/MC/ELF/relocation-alias.s
M llvm/test/MC/X86/gotpcrelx.s
M llvm/test/MC/X86/reloc-directive-elf-64.s
Log Message:
-----------
[X86,MC] Add relocation R_X86_64_REX2_GOTPCRELX (#106681)
For
mov name at GOTPCREL(%rip), %reg
test %reg, name at GOTPCREL(%rip)
binop name at GOTPCREL(%rip), %reg
where binop is one of adc, add, and, cmp, or, sbb, sub, xor
instructions, add
`R_X86_64_REX2_GOTPCRELX`/`R_X86_64_CODE_4_GOTPCRELX` = 43
if the instruction starts at 4 bytes before the relocation offset. It
similar to R_X86_64_GOTPCRELX.
Linker can treat `R_X86_64_REX2_GOTPCRELX`/`R_X86_64_CODE_4_GOTPCRELX`
as `R_X86_64_GOTPCREL` or convert the above instructions to
lea name(%rip), %reg
mov $name, %reg
test $name, %reg
binop $name, %reg
if the first byte of the instruction at the relocation `offset - 4` is
`0xd5` (namely, encoded w/ REX2 prefix) when possible.
Binutils patch:
https://github.com/bminor/binutils-gdb/commit/3d5a60de52556f6a53d71d7e607c6696450ae3e4
Binutils mailthread:
https://sourceware.org/pipermail/binutils/2023-December/131462.html
ABI discussion: https://groups.google.com/g/x86-64-abi/c/KbzaNHRB6QU
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: 6cfe6a6b3e9578be80120add7fbe19506f747196
https://github.com/llvm/llvm-project/commit/6cfe6a6b3e9578be80120add7fbe19506f747196
Author: Georgi Mirazchiyski <georgi.mirazchiyski at codeplay.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[NFC][AMDGPU] Assert no bad shift operations will happen (#108416)
The assumption in the asserts is based on the fact that no SGPR/VGPR
register Arg mask in the ISelLowering and Legalizer can equal zero. They
are implicitly set to ~0 by default (meaning non-masked) or explicitly
to a non-zero value.
The `optimizeCompareInstr` case is different from the above described.
It requires the mask to be a power-of-two because it's a special-case
optimization, hence in this case we still cannot have an invalid shift.
This commit also silences static analysis tools wrt potential bad shifts
that could result from the output of `countr_zero(Mask)`.
Commit: 5dc15ddf575978e0115b1a6edacb59f056792a80
https://github.com/llvm/llvm-project/commit/5dc15ddf575978e0115b1a6edacb59f056792a80
Author: Georgi Mirazchiyski <georgi.mirazchiyski at codeplay.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
Log Message:
-----------
[AMDGPU] Default-initialize uninitialized class member variables (#108428)
Commit: 4f8e76684f4c1e67726222c35f173ef722464a7e
https://github.com/llvm/llvm-project/commit/4f8e76684f4c1e67726222c35f173ef722464a7e
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
Log Message:
-----------
[AsmPrinter] Do not emit label instructions after the function body if the target is SPIR-V (#107013)
AsmPrinter always creates a symbol for the end of function if valid
debug info is present. However, this breaks SPIR-V target's output,
because SPIR-V specification allows label instructions only inside a
block, not after the function body (see
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpLabel).
This PR proposes to disable emission of label instructions after the
function body if the target is SPIR-V.
This PR is a fix of the
https://github.com/llvm/llvm-project/issues/102732 issue.
Commit: 497759e872a53964a54db941f3a1ed74446c5ed4
https://github.com/llvm/llvm-project/commit/497759e872a53964a54db941f3a1ed74446c5ed4
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
A lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegistersSVEOnly.py
Log Message:
-----------
[lldb][AArch64] Create Neon subregs when XML only includes SVE (#108365)
Fixes #107864
QEMU decided that when SVE is enabled it will only tell us about SVE
registers in the XML, and not include Neon registers. On the grounds
that the Neon V registers can be read from the bottom 128 bits of a SVE
Z register (SVE's vector length is always >= 128 bits).
To support this we create sub-registers just as we do for S and D
registers of the V registers. Except this time we use part of the Z
registers.
This change also updates our fallback for registers with unknown types
that are > 128 bit. This is detailed in
https://github.com/llvm/llvm-project/issues/87471, though that covers
more than this change fixes.
We'll now treat any register of unknown type that is >= 128 bit as a
vector of bytes. So that the user gets to see something
even if the order might be wrong.
And until lldb supports vector and union types for registers, this is
also the only way we can get a value to apply the sub-reg to, to make
the V registers.
Commit: c30fa3cde755e7519f0962f581868a09da1ea130
https://github.com/llvm/llvm-project/commit/c30fa3cde755e7519f0962f581868a09da1ea130
Author: Georgi Mirazchiyski <georgi.mirazchiyski at codeplay.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU] Fix has_single_bit assertion for Mask in SIInstrInfo (#109785)
Convert the `int64_t` Mask to `uint64_t` for `llvm::has_single_bit` to
compile.
Commit: 029b9b611d8becf04f4c525ab2b70e956b4b186d
https://github.com/llvm/llvm-project/commit/029b9b611d8becf04f4c525ab2b70e956b4b186d
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/CMake.rst
Log Message:
-----------
[llvm][docs] Improve formatting of ENABLE_PROJECTS/RUNTIMES description
* Add line breaks so it's clear what should be passed to CMake.
* Make the note into an RST note block.
* Fix a couple of markdown style plain text markers.
Commit: c1826aeef353bf4bd8b181b47a0dbb1f1af93836
https://github.com/llvm/llvm-project/commit/c1826aeef353bf4bd8b181b47a0dbb1f1af93836
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Add new helper hooks for RelayoutOp (#109642)
Implements two helper hooks for PackOp and UnPackOP, `getAllOuterDims`
and `getTiledOuterDims`, and adds them to RelayoutOp (that both PackOp
an UnPackOp inherit from).
This improves code re-use and also clarifies the meaning of "outer dims"
and "tiled outer dims".
Commit: 3e3780ef6ab5902cd1763e28bb143e47091bd23a
https://github.com/llvm/llvm-project/commit/3e3780ef6ab5902cd1763e28bb143e47091bd23a
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-bf16-converts.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Implement nxvf32 fpround to nxvbf16. (#107420)
Commit: 8ba334bc4ad1e20c8201b85ed0a3e3b87bc47fe1
https://github.com/llvm/llvm-project/commit/8ba334bc4ad1e20c8201b85ed0a3e3b87bc47fe1
Author: Dominik Montada <dominik.montada at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties-conflict.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties.mir
M llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
Log Message:
-----------
[MIR] Allow overriding isSSA, noPhis, noVRegs in MIR input (#108546)
Allow setting the computed properties IsSSA, NoPHIs, NoVRegs for MIR
functions in MIR input. The default value is still the computed value.
If the property is set to false, the computed result is ignored. Conflicting
values (e.g. setting IsSSA where the input MIR is clearly not SSA) lead to
an error.
Closes #37787
Commit: db054a197002c4d6b2c568d7c36d86f5fccade2d
https://github.com/llvm/llvm-project/commit/db054a197002c4d6b2c568d7c36d86f5fccade2d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/test/CodeGen/AArch64/sme-streaming-mode-changing-call-disable-stackslot-scavenging.ll
Log Message:
-----------
[AArch64][SME] Fix ADDVL addressing to scavenged stackslot. (#109674)
In https://reviews.llvm.org/D159196 we avoided stackslot scavenging
when there was no FP available. But in the case where FP is available
we need to actually prefer using the FP over the BP.
This change affects more than just SME, but it should be a general
improvement, since any slot above the (address pointed to by) FP
is always closer to FP than BP, so it makes sense to always favour
using the FP to address it when the FP is available.
This also fixes the issue for SME where this is not just preferred
but required.
Commit: 3073c3c2290a6d9b12fbaefa40dd22eef6312895
https://github.com/llvm/llvm-project/commit/3073c3c2290a6d9b12fbaefa40dd22eef6312895
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
A llvm/test/CodeGen/AArch64/sincos-stack-slots.ll
Log Message:
-----------
[SDAG] Avoid creating redundant stack slots when lowering FSINCOS (#108401)
When lowering `FSINCOS` to a library call (that takes output pointers)
we can avoid creating new stack allocations if the results of the
`FSINCOS` are being stored. Instead, we can take the destination
pointers from the stores and pass those to the library call.
---
Note: As a NFC this also adds (and uses) `RTLIB::getFSINCOS()`.
Commit: 3ec5e74c0dc99095f5961a31421c7adaf2860ec8
https://github.com/llvm/llvm-project/commit/3ec5e74c0dc99095f5961a31421c7adaf2860ec8
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fix layering for 127349fcba81646389e4b8202b35405a5fdbef47
Commit: 66c8dce82e60ebd22bbe6ce7c1550ae6de057625
https://github.com/llvm/llvm-project/commit/66c8dce82e60ebd22bbe6ce7c1550ae6de057625
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/TableGen/Record.h
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
A llvm/test/TableGen/listflatten-error.td
A llvm/test/TableGen/listflatten.td
Log Message:
-----------
[TableGen] Add a !listflatten operator to TableGen (#109346)
Add a !listflatten operator that will transform an input list of type
`list<list<X>>` to `list<X>` by concatenating elements of the
constituent lists of the input argument.
Commit: 12033e550b186f3b3e4d2ca3ce9cfc3d3a3fa6e1
https://github.com/llvm/llvm-project/commit/12033e550b186f3b3e4d2ca3ce9cfc3d3a3fa6e1
Author: Bevin Hansson <59652494+bevin-hansson at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
A llvm/test/CodeGen/SPARC/salvage-debug-isel.ll
M llvm/test/CodeGen/X86/pr57673.ll
Log Message:
-----------
[ISelDAG] Salvage debug info at isel by referring to frame indices. (#109126)
We can refer to frame index locations when salvaging debug info
for certain nodes, which prevents the compiler from optimizing
out the location.
Commit: b47d1787b51f55d69ef1b4f88e72cd54af451649
https://github.com/llvm/llvm-project/commit/b47d1787b51f55d69ef1b4f88e72cd54af451649
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][vector] Refine vectorisation of tensor.extract (#109580)
This PR fixes a bug in `isLoopInvariantIdx`. It makes sure that the
following case is vectorised as `vector.gather` (as opposed to
attempting a contiguous load):
```mlir
func.func @index_from_output_column_vector_gather_load(%src: tensor<8x128xf32>) -> tensor<8x1xf32> {
%c0 = arith.constant 0 : index
%0 = tensor.empty() : tensor<8x1xf32>
%res = linalg.generic {
indexing_maps = [#map],
iterator_types = ["parallel", "parallel"]
} outs(%0 : tensor<8x1xf32>) {
^bb0(%arg1: f32):
%1 = linalg.index 0 : index
%extracted = tensor.extract %src[%1, %c0] : tensor<8x128xf32>
linalg.yield %extracted : f32
} -> tensor<8x1xf32>
return %res : tensor<8x1xf32>
}
```
Specifically, when looking for loop-invariant indices in
`tensor.extract` Ops, any `linalg.index` Op that's used in address
colcluation should only access loop dims that are == 1. In the example
above, the following does not meet that criteria:
```mlir
%1 = linalg.index 0 : index
```
Note that this PR also effectively addresses the issue fixed in #107922,
i.e. exercised by:
* `@vectorize_nd_tensor_extract_load_1d_column_vector_using_gather_load`
`getNonUnitLoopDim` introduced in #107922 is still valid though. In
fact, it is required to identify that the following case is a contiguous
load:
```mlir
func.func @index_from_output_column_vector_contiguous_load(%src: tensor<8x128xf32>) -> tensor<8x1xf32> {
%c0 = arith.constant 0 : index
%0 = tensor.empty() : tensor<8x1xf32>
%res = linalg.generic {
indexing_maps = [#map],
iterator_types = ["parallel", "parallel"]
} outs(%0 : tensor<8x1xf32>) {
^bb0(%arg1: f32):
%1 = linalg.index 0 : index
%extracted = tensor.extract %src[%c0, %1] : tensor<8x128xf32>
linalg.yield %extracted : f32
} -> tensor<8x1xf32>
return %res : tensor<8x1xf32>
}
```
Some logic is still missing to lower the above to
`vector.transfer_read`, so it is conservatively lowered to
`vector.gather` instead (see TODO in
`getTensorExtractMemoryAccessPattern`).
There's a few additional changes:
* `getNonUnitLoopDim` is simplified and renamed as
`getTrailingNonUnitLoopDimIdx`, additional comments are added (note
that the functionality didn't change);
* extra comments in a few places, variable names in comments update to
use Markdown (which is the preferred approach in MLIR).
This is a follow-on for:
* https://github.com/llvm/llvm-project/pull/107922
* https://github.com/llvm/llvm-project/pull/102321
Commit: 106e4506ce6084e10353073d8880e2f736b74981
https://github.com/llvm/llvm-project/commit/106e4506ce6084e10353073d8880e2f736b74981
Author: David Pagan <dave.pagan at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[OpenMP][Docs] Update OpenMP release notes with 'omp scope' (#109752)
Release notes: added 'omp scope' directive to "OpenMP Support" section
of "What's New in Clang"
Commit: ebbf664aa31ac51c43a345a8a3d0734c54be7c4b
https://github.com/llvm/llvm-project/commit/ebbf664aa31ac51c43a345a8a3d0734c54be7c4b
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
Log Message:
-----------
[AMDGPU] Use shared prefix in GFX12 barrier test
Commit: 57bee1e4322d34f9760563081f9c10b6850bc2bf
https://github.com/llvm/llvm-project/commit/57bee1e4322d34f9760563081f9c10b6850bc2bf
Author: Xing Guo <higuoxing+github at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
A llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC.s
R llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC8.s
Log Message:
-----------
[JITLink] Add support for R_X86_64_PC16 relocation type. (#109630)
This patch adds support for R_X86_64_PC16 relocation type and
x86_64::Delta16 edge kind. This patch also adds missing test cases for
R_X86_64_PC32, R_X86_64_PC64 relocation types.
Commit: 02a334de6690202154ef09456c581618ff290f9a
https://github.com/llvm/llvm-project/commit/02a334de6690202154ef09456c581618ff290f9a
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
Log Message:
-----------
[SPIR-V] Fix bad insertion for type/id MIR (#109686)
Those instructions were inserted either after the instruction using it,
or in the middle of the module.
The first directly causes an issue. The second causes a more subtle
issue: the first type the type is inserted, the emission is fine, but
the second times, the first instruction is reused, without checking its
position in the function. This can lead to the second usage dominating
the definition.
In SPIR-V, types are usually in the header, above all code definition,
but at this stage I don't think we can, so what I do instead is to emit
it in the first basic block.
This commit reduces the failed tests with expensive checks from 107 to
71.
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: fe7bc872aad83fc0d5cf998230df752e73bb696d
https://github.com/llvm/llvm-project/commit/fe7bc872aad83fc0d5cf998230df752e73bb696d
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/DebugInfo/Generic/debug-ranges-duplication.ll
Log Message:
-----------
[DebugInfo][z/OS] XFAIL debug-ranges-duplication.ll on z/OS (#109681)
Same fix was provided for AIX in commit
704da919bafa5b088223f9d77424f24ae754539e.
The issue is unsupported DWARF 5 section with the following assertion:
`Assertion failed: Section && "Cannot switch to a null section!", file:
llvm/lib/MC/MCStreamer.cpp, line: 1266 `
Commit: 0de1e3e787c6d78b87ccb865ba2f2daf8d8e4ecc
https://github.com/llvm/llvm-project/commit/0de1e3e787c6d78b87ccb865ba2f2daf8d8e4ecc
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/tools/llvm-ctxprof-util/llvm-ctxprof-util.cpp
Log Message:
-----------
[;SystemZ][z/OS] Fix llvm-ctxprof to open input files in text mode (#109691)
Reading text files on z/OS relies on auto conversion to handle
ASCII/EBCDIC correctly. For this to work files need to be opened in text
mode is that is the type of the file. This PR fixes `llvm-ctxprof`
utility in this regards which in turn fixes the following LIT failure on
z/OS:
`FAIL: LLVM :: Analysis/CtxProfAnalysis/flatten-zero-path.ll`
Commit: 622ae7ffa432ca5985cf1655cf499e04b289bbf2
https://github.com/llvm/llvm-project/commit/622ae7ffa432ca5985cf1655cf499e04b289bbf2
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-insr.ll
Log Message:
-----------
[LLVM][InstCombine][AArch64] sve.insr(splat(x), x) ==> splat(x) (#109445)
Fixes https://github.com/llvm/llvm-project/issues/100497
Commit: 216e1b90c4a988880b772b8d152769f7d0cac0c6
https://github.com/llvm/llvm-project/commit/216e1b90c4a988880b772b8d152769f7d0cac0c6
Author: davidtrevelyan <davidtrevelyan at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.h
Log Message:
-----------
[rtsan] Remove std::variant from rtsan diagnostics (#109786)
Following issue #109529 and PR
#109715, this PR removes the
`std::variant` in rtsan's diagnostics code, in favour of a solution by
`enum` without the C++ runtime.
Commit: b1e4656e8ee3289dc5f3139fc8eb33152f96bfe6
https://github.com/llvm/llvm-project/commit/b1e4656e8ee3289dc5f3139fc8eb33152f96bfe6
Author: Pavel Skripkin <paskripkin at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ProgramState.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h
M clang/lib/StaticAnalyzer/Core/ProgramState.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
Log Message:
-----------
[NFC][analyzer] Make `invalidateRegions` accept `Stmt` instead of `Expr` (#109792)
As was reported
[here](https://github.com/llvm/llvm-project/pull/103714#pullrequestreview-2238037812),
`invalidateRegions` should accept `Stmt` instead of `Expr`. This
conversion is possible, since `Expr` was anyway converted back to `Stmt`
later.
This refactoring is needed to fix another FP related to use of inline
assembly. The fix would be to change `State->bindLoc` to
`state->invalidateRegions` inside inline assembly visitor, since
`bindLoc` only binds to offset 0, which is not really correct semantics
in case of inline assembly.
Commit: 3fbf6f8bb183ad8b9157e50c442479f4ca7a9b8d
https://github.com/llvm/llvm-project/commit/3fbf6f8bb183ad8b9157e50c442479f4ca7a9b8d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[LV] Remove more references of unrolled parts after 57f5d8f2fe.
Continue to clean up some now stale references of unroll parts and
related terminology as pointed out post-commit for 06c3a7d.
Commit: 8b5e841487976ecc4233227fdd069f5a5f4443f0
https://github.com/llvm/llvm-project/commit/8b5e841487976ecc4233227fdd069f5a5f4443f0
Author: Chao Chen <chao.chen at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
Log Message:
-----------
[MLIR][XeGPU] Updates XeGPU TensorDescAttr and Refine Gather/Scatter definition (#109675)
Bring back #109144 with fixes to VectorToXeGPU
Commit: 36757613b73908f055674a8df0b51cc00aa04373
https://github.com/llvm/llvm-project/commit/36757613b73908f055674a8df0b51cc00aa04373
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
R llvm/test/CodeGen/NVPTX/intrin-nocapture.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
Log Message:
-----------
[NVVM] Upgrade nvvm.ptr.* intrinics to addrspace cast (#109710)
Remove the following intrinsics which can be trivially replaced with an
`addrspacecast`
* llvm.nvvm.ptr.gen.to.global
* llvm.nvvm.ptr.gen.to.shared
* llvm.nvvm.ptr.gen.to.constant
* llvm.nvvm.ptr.gen.to.local
* llvm.nvvm.ptr.global.to.gen
* llvm.nvvm.ptr.shared.to.gen
* llvm.nvvm.ptr.constant.to.gen
* llvm.nvvm.ptr.local.to.gen
Also, cleanup the NVPTX lowering of `addrspacecast` making it more
concise.
Commit: bcbdf7ad6b571d11c102d018c78ee0fbf71e3e2c
https://github.com/llvm/llvm-project/commit/bcbdf7ad6b571d11c102d018c78ee0fbf71e3e2c
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
Log Message:
-----------
[RISCV][TTI/SLP] Add test coverage for select of constants costing
Provides coverage for an upcoming change which accounts for the cost
of materializing the vector constants in the vector select.
Commit: 31ac400e451b5dcbf11a3ece94d58dc3edf24e14
https://github.com/llvm/llvm-project/commit/31ac400e451b5dcbf11a3ece94d58dc3edf24e14
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Remove another reference of unrolled parts after 57f5d8f2fe.
Continue to clean up some now stale references of unroll parts and
related terminology as pointed out post-commit for 06c3a7d.
Commit: fa17977c315062646d4d1e01262d68dd69313e61
https://github.com/llvm/llvm-project/commit/fa17977c315062646d4d1e01262d68dd69313e61
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
Log Message:
-----------
[libc][bazel] Remove specializations from libc_math_function. (#109802)
There are no more specializations `libc/src/math/x86_64` or
`libc/src/math/aarch64` anymore. All implementations are going through
the generic implementation.
Commit: 99ade15d192db4afa897a7052a9c73dd42c2b88c
https://github.com/llvm/llvm-project/commit/99ade15d192db4afa897a7052a9c73dd42c2b88c
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
M compiler-rt/test/sanitizer_common/TestCases/Linux/prctl.cpp
Log Message:
-----------
Revert "[compiler-rt] prctl interception update, SECCOMP_MODE_FILTER support. (#107722)"
This reverts commit b75174d05aa033a382d4c088e96e068a774f46da.
Does not build on Android, see comments on
https://github.com/llvm/llvm-project/pull/107722
Commit: fda01437af339c87ecd226596dd1b5f6d2c6cbfa
https://github.com/llvm/llvm-project/commit/fda01437af339c87ecd226596dd1b5f6d2c6cbfa
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Frontend/Rewrite/RewriteObjC.cpp
Log Message:
-----------
[Rewrite] Use SmallSetVector (NFC) (#109746)
We can combine:
SmallVector<ValueDecl *, 8> BlockByCopyDecls;
llvm::SmallPtrSet<ValueDecl *, 8> BlockByCopyDeclsPtrSet;
into:
llvm::SmallSetVector<ValueDecl *, 8> BlockByCopyDecls;
Likewise, we can combine:
SmallVector<ValueDecl *, 8> BlockByRefDecls;
llvm::SmallPtrSet<ValueDecl *, 8> BlockByRefDeclsPtrSet;
into:
llvm::SmallSetVector<ValueDecl *, 8> BlockByRefDecls;
Commit: 36dce5091e384087f5d1ceaf3777ac14f41087e4
https://github.com/llvm/llvm-project/commit/36dce5091e384087f5d1ceaf3777ac14f41087e4
Author: spupyrev <spupyrev at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
Log Message:
-----------
[CodeLayout][NFC] Format and minor refactoring of MBP (#109729)
This PR has two (NFC) commits:
- clang-format MBP
- move a part of tail duplication and block aligning into helper
functions for better readability.
Commit: f12d72d9c95ea2cd82d3e2a70c8cd5d5e88e2060
https://github.com/llvm/llvm-project/commit/f12d72d9c95ea2cd82d3e2a70c8cd5d5e88e2060
Author: David Green <david.green at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/PtrUseVisitor.h
Log Message:
-----------
[PtrInfo] Use plain pointer over 'PointerIntPair<Instruction *, 1, bool>'. NFC (#109772)
This PtrInfo holds a pointer and whether it has been set. We can
represent this sentinal value as a nullptr, as we would for most
pointers. This assumes that the value is never set to nullptr, but from
the uses that appears to be true and already assumed.
Commit: d075debc508898d5f365f8e909c54d6f4edada85
https://github.com/llvm/llvm-project/commit/d075debc508898d5f365f8e909c54d6f4edada85
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
Log Message:
-----------
[AMDGPU] Fix chain handling when lowering barrier intrinsics (#109799)
Previously we would fail an assertion in RemoveNodeFromCSEMaps after
lowering:
t3: ch = llvm.amdgcn.s.barrier.join t0, TargetConstant:i64<2973>,
Constant:i32<0>
to:
t6: ch = S_BARRIER_JOIN_IMM TargetConstant:i32<0>
Commit: d4a38c8ff5c993e14c42895b51a47272fb03a857
https://github.com/llvm/llvm-project/commit/d4a38c8ff5c993e14c42895b51a47272fb03a857
Author: Usman Nadeem <mnadeem at quicinc.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
Log Message:
-----------
[DFAJumpThreading] Handle select unfolding when user phi is not a dir… (#109511)
…ect successor
Previously the code assumed that the select instruction is defined in a
block that is a direct predecessor of the block where the PHINode uses
it. So, we were hitting an assertion when we tried to access the def
block as an incoming block for the user phi node.
This patch handles that case by using the correct end block and creating
a new phi node that aggregates both the values of the select in that end
block, and then using that new unfolded phi to overwrite the original
user phi node.
Fixes #106083
Change-Id: Ie471994cca232318f74a6e6438efa21e561c2dc0
Commit: 679c9717dfc9687a3bca78b45d9fd104b67e16f9
https://github.com/llvm/llvm-project/commit/679c9717dfc9687a3bca78b45d9fd104b67e16f9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
Log Message:
-----------
[clang][bytecode] Fix vector shifts on big-endian systems (#109800)
For shifts, the LHS and RHS element types might be different. The
variable naming here could probably use some love now, but I'm trying to
fix this as fast as possible.
See the discussion in https://github.com/llvm/llvm-project/pull/108949
Commit: 206408732bca2ef464732a39c8319d47c8a1dbea
https://github.com/llvm/llvm-project/commit/206408732bca2ef464732a39c8319d47c8a1dbea
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/include/lldb/Symbol/UnwindPlan.h
Log Message:
-----------
[lldb][NFC] Add a missing setter method for UnwindPlans (#109751)
The UnwindPlan class has getter and setter methods for specifying an
abstract register location, but it doesn't have a setter for a DWARF
Expression register location. This hasn't been needed for any of the
UnwindPlans that we do in mainline lldb yet, but it is used in the Swift
language SwiftLanguageRuntime plugin which creates UnwindPlan for async
functions. While it's currently unused on main branch, this is a
straightforward setter in the same form as the others, the only caveat
being that it doesn't own the dwarf expression bytes, it has a pointer
to them.
Commit: 7773243d9916f98ba0ffce0c3a960e4aa9f03e81
https://github.com/llvm/llvm-project/commit/7773243d9916f98ba0ffce0c3a960e4aa9f03e81
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/X86/peek-through-shuffle.ll
R llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll
R llvm/test/Transforms/SLPVectorizer/X86/phi-undef-input.ll
R llvm/test/Transforms/SLPVectorizer/X86/postponed_gathers.ll
R llvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll
R llvm/test/Transforms/SLPVectorizer/X86/pr31599.ll
R llvm/test/Transforms/SLPVectorizer/X86/reduction-gather-non-scheduled-extracts.ll
R llvm/test/Transforms/SLPVectorizer/X86/reduction-modified-values.ll
R llvm/test/Transforms/SLPVectorizer/X86/reorder-clustered-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/reordered-top-scalars.ll
R llvm/test/Transforms/SLPVectorizer/X86/reordering-single-phi.ll
R llvm/test/Transforms/SLPVectorizer/X86/reused-buildvector-matching-vectorized-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/root-trunc-extract-reuse.ll
R llvm/test/Transforms/SLPVectorizer/X86/same-scalar-in-same-phi-extract.ll
R llvm/test/Transforms/SLPVectorizer/X86/scalarazied-result.ll
R llvm/test/Transforms/SLPVectorizer/X86/scalarization-overhead.ll
R llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder2.ll
R llvm/test/Transforms/SLPVectorizer/X86/shuffle-multivector.ll
R llvm/test/Transforms/SLPVectorizer/X86/shufflebuilder-bug.ll
R llvm/test/Transforms/SLPVectorizer/X86/stores-non-ordered.ll
R llvm/test/Transforms/SLPVectorizer/X86/unknown-entries.ll
R llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll
A llvm/test/Transforms/SLPVectorizer/peek-through-shuffle.ll
A llvm/test/Transforms/SLPVectorizer/phi-node-bitwidt-op-not.ll
A llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll
A llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll
A llvm/test/Transforms/SLPVectorizer/pr31599-inseltpoison.ll
A llvm/test/Transforms/SLPVectorizer/pr31599.ll
A llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
A llvm/test/Transforms/SLPVectorizer/reduction-modified-values.ll
A llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll
A llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll
A llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
A llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
A llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll
A llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll
A llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
A llvm/test/Transforms/SLPVectorizer/scalarization-overhead.ll
A llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
A llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll
A llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll
A llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll
A llvm/test/Transforms/SLPVectorizer/unknown-entries.ll
A llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
Log Message:
-----------
[SLP] Move more X86 tests to common directory (#109821)
Some of the tests from the X86 directory can be generalized to improve
coverage for other architectures
Commit: fe6a3d46aa658fdd1e9a6cbb2031a597a3e59536
https://github.com/llvm/llvm-project/commit/fe6a3d46aa658fdd1e9a6cbb2031a597a3e59536
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
M libc/docs/gpu/support.rst
M libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/src/stdio/gpu/CMakeLists.txt
A libc/src/stdio/gpu/rename.cpp
M libc/utils/gpu/server/rpc_server.cpp
Log Message:
-----------
[libc] Implement the 'rename' function on the GPU (#109814)
Summary:
Straightforward implementation like the other `stdio.h` functions.
Commit: 8e68a512ef568324da60c8b2705e9b087d06ebcf
https://github.com/llvm/llvm-project/commit/8e68a512ef568324da60c8b2705e9b087d06ebcf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/pmulh.ll
Log Message:
-----------
[X86] Add test coverage for #109790
Commit: 01be0252c834bc7be222057049d697f488493543
https://github.com/llvm/llvm-project/commit/01be0252c834bc7be222057049d697f488493543
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combinePMULH - simplify pattern matching with SDPatternMatch. NFC.
Commit: 9e60a6ad4242274c39242079d5351fcb9d6d99e6
https://github.com/llvm/llvm-project/commit/9e60a6ad4242274c39242079d5351fcb9d6d99e6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combinePMULH - pull out repeated IsTruncateFree helper. NFC.
Commit: 406a2128f57b1e86748cd6de6d3eab6b1e2db2ad
https://github.com/llvm/llvm-project/commit/406a2128f57b1e86748cd6de6d3eab6b1e2db2ad
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/pmulh.ll
Log Message:
-----------
[X86] combinePMULH - we can treat constant vectors as freely truncatable.
Fixes #109790
Commit: e64673d3174af941eb3c9f1ad822792154aa1d31
https://github.com/llvm/llvm-project/commit/e64673d3174af941eb3c9f1ad822792154aa1d31
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Treat insert_subvector into undef with index==0 as legal. (#109745)
Regardless of fixed and scalable type. We can always use subreg ops.
We don't need to do any container conversion.
Commit: c6bf59f26b2d74474a66182db6ebd576273bfb00
https://github.com/llvm/llvm-project/commit/c6bf59f26b2d74474a66182db6ebd576273bfb00
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
Log Message:
-----------
[X86] Add test coverage for #109272
Commit: 04b443e77845cd20ab5acc4356cee509316135dd
https://github.com/llvm/llvm-project/commit/04b443e77845cd20ab5acc4356cee509316135dd
Author: jimingham <jingham at apple.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/use/python-reference.rst
M lldb/examples/python/cmdtemplate.py
M lldb/examples/python/templates/parsed_cmd.py
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Utility/CompletionRequest.h
M lldb/source/Commands/CommandObjectCommands.cpp
M lldb/source/Interpreter/Options.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/test/API/commands/command/script/add/TestAddParsedCommand.py
M lldb/test/API/commands/command/script/add/test_commands.py
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
Log Message:
-----------
Add the ability to define custom completers to the parsed_cmd template. (#109062)
If your arguments or option values are of a type that naturally uses one
of our common completion mechanisms, you will get completion for free.
But if you have your own custom values or if you want to do fancy things
like have `break set -s foo.dylib -n ba<TAB>` only complete on symbols
in foo.dylib, you can use this new mechanism to achieve that.
Commit: 090755234e5033de67be994e99e31f4d13dcdcc5
https://github.com/llvm/llvm-project/commit/090755234e5033de67be994e99e31f4d13dcdcc5
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan.cpp
Log Message:
-----------
[rtsan] Refactor initialization state to prevent hangs (#109830)
Move to tri state (Uninitialized, Initialized, Initializing) for our
init state. We currently just have 2 (Uninitialized and Initialized).
Commit: f4042077e2e3946ee35c1df8cab8237de6086480
https://github.com/llvm/llvm-project/commit/f4042077e2e3946ee35c1df8cab8237de6086480
Author: vporpo <vporpodas at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement a few Instruction member functions (#109820)
This patch implements a few sandboxir::Instruction predicate functions.
Commit: 234193bae6cf8b19703c6e543b100517bb99a9f7
https://github.com/llvm/llvm-project/commit/234193bae6cf8b19703c6e543b100517bb99a9f7
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorize-convolution.mlir
Log Message:
-----------
[mlir][linalg] Vectorization support for convolution of i1 type (#109480)
Normally convolutions present with the following linalg op region
```
^bb0(%arg14: i4, %arg15: i4, %arg16: i4):
%17 = arith.muli %arg14, %arg15 : i4
%18 = arith.addi %arg16, %17 : i4
linalg.yield %18 : i4
```
However, for i1 due to strength reduction we get something like
```
^bb0(%arg14: i1, %arg15: i1, %arg16: i1):
%17 = arith.andi %arg14, %arg15 : i1
%18 = arith.ori %arg16, %17 : i1
linalg.yield %18 : i1
```
This PR updates the logic to support this region for i1 types.
Commit: 26029d77a57cb4aaa1479064109e985a90d0edd8
https://github.com/llvm/llvm-project/commit/26029d77a57cb4aaa1479064109e985a90d0edd8
Author: Tex Riddell <texr at microsoft.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
A llvm/test/CodeGen/DirectX/atan2.ll
A llvm/test/CodeGen/DirectX/atan2_error.ll
Log Message:
-----------
[DirectX] Add atan2 intrinsic and expand for DXIL backend (p1) (#108865)
This change is part of this proposal:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
This preliminary work adds the intrinsic to llvm and expands using atan
intrinsic for DXIL backend, since DXIL has no atan2 op.
Part 1 for Implement the atan2 HLSL Function #70096.
Commit: 12285cca5ed713dfd483bd96422a5607b8af0085
https://github.com/llvm/llvm-project/commit/12285cca5ed713dfd483bd96422a5607b8af0085
Author: Daniel Rodríguez Troitiño <drodriguez at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp
M llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h
A llvm/test/tools/dsymutil/X86/dwarf5-many-include-directories.test
Log Message:
-----------
[DWARF] Use ULEB128 and not just one byte for directory indices (#109067)
According to the standard `DW_LNCT_directory_index` can be `data1`,
`data2`, or `udata` (see 6.2.4.1). The code was using `data1`, but this
limits the number of directories to 256, even if the variable holding
the directory index is a `uint64_t`. `dsymutil` was hitting an assertion
when trying to write directory indices higher than 255.
Modify the classic and the parallel DWARF linkers to use `udata` and
encode the directory indices as ULEB128 and provide a test that has more
than 256 directories to check the changes are working as expected.
For people that were using `dsymutil` with CUs that had between 128-256
directories, this will mean that for those indices 2 bytes will be used
now, instead of just one.
Commit: 6dfeea3f865cff0c1e3ca19aa0e77f379809b2a9
https://github.com/llvm/llvm-project/commit/6dfeea3f865cff0c1e3ca19aa0e77f379809b2a9
Author: Farzon Lotfi <1802579+farzonl at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
R llvm/test/CodeGen/DirectX/atan2.ll
R llvm/test/CodeGen/DirectX/atan2_error.ll
Log Message:
-----------
Revert "[DirectX] Add atan2 intrinsic and expand for DXIL backend (p1)" (#109842)
Reverts llvm/llvm-project#108865
Broke the Docs build
Commit: 312f73765b29db468cd282130d1b519ed3eeae96
https://github.com/llvm/llvm-project/commit/312f73765b29db468cd282130d1b519ed3eeae96
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lld/test/wasm/unsupported-pic-relocations.s
M lld/test/wasm/unsupported-pic-relocations64.s
M lld/wasm/Relocations.cpp
Log Message:
-----------
[lld][WebAssembly] Don't report relocation error when linking with -r/--relocatable (#109822)
Followup to #104926.
We ran into issues on the emscripten waterfall where relocation against
`__dso_handle` were being reported as errors even though
`-r/--relocatable` was being used to generate object file output rather
than executable output.
Commit: a977b9460f8f007a7dedd9197adc7d76bb95b0b6
https://github.com/llvm/llvm-project/commit/a977b9460f8f007a7dedd9197adc7d76bb95b0b6
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
M compiler-rt/test/sanitizer_common/TestCases/Linux/prctl.cpp
Log Message:
-----------
Reapply [compiler-rt] prctl interception update, SECCOMP_MODE_FILTER … (#109834)
…support. #107722
Commit: 6d3d5f30bd58af6d16d0b4b7d32dc3ead1e098ec
https://github.com/llvm/llvm-project/commit/6d3d5f30bd58af6d16d0b4b7d32dc3ead1e098ec
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-09-25 (Wed, 25 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/revec-fix-109835.ll
Log Message:
-----------
[SLP][REVEC] getWidenedType should be used instead of FixedVectorType::get. (#109843)
reference: https://github.com/llvm/llvm-project/issues/109835
Commit: 71ca9fcb8dc9ea0e1e3a4a47820edc78c398a85e
https://github.com/llvm/llvm-project/commit/71ca9fcb8dc9ea0e1e3a4a47820edc78c398a85e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/tools/llvm-reduce/ReducerWorkItem.cpp
M llvm/unittests/MI/LiveIntervalTest.cpp
Log Message:
-----------
llvm-reduce: Don't print verifier failed machine functions (#109673)
This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness of of
the instructions it's deleting, it produces quite a lot of verifier
errors.
Commit: a6bdf3face377ee7ea84a02bada8a7e2ff380fe8
https://github.com/llvm/llvm-project/commit/a6bdf3face377ee7ea84a02bada8a7e2ff380fe8
Author: Charlie Barto <chbarto at microsoft.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/test/asan/lit.cfg.py
Log Message:
-----------
[asan][windows][tests] support MSVC compiler-id in asan tests (#109706)
This follows up on https://github.com/llvm/llvm-project/pull/108255 to
allow actually running the test suite with MSVC. Note, however, that
MSVC can't yet build compiler-rt, most tests don't yet pass with msvc,
and building and testing with different compilers is ill-supported.
Follow ups will fix the first two issues, the third is future work.
Note that `/Zi` is removed from the clang-cl command line, but lit as a
whole adds `-gcodeview`, so there should still be debug info.
Commit: c95583f15f77a2f4fed4b520b2bcf7b442cbc4b3
https://github.com/llvm/llvm-project/commit/c95583f15f77a2f4fed4b520b2bcf7b442cbc4b3
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Add createPtrAdd helper (NFC).
Preparation for https://github.com/llvm/llvm-project/pull/106431.
Commit: 9830156f623c56062bf6df1b4c4b4bd8ab5bd57c
https://github.com/llvm/llvm-project/commit/9830156f623c56062bf6df1b4c4b4bd8ab5bd57c
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
A llvm/test/MC/AMDGPU/gfx11_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] add true16 and fake16 test file for vop3 instructions (#109695)
duplicating mc test, and updating proper flag for true16 and fake16 test
file for vop3 instructions. This is preparing for the up-coming VOP3
true16 changes
Commit: ec31f76df11d624699a7b2d4d9da052b4cc47452
https://github.com/llvm/llvm-project/commit/ec31f76df11d624699a7b2d4d9da052b4cc47452
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/Support/OptionStrCmp.h
M llvm/test/TableGen/listflatten-error.td
M llvm/test/TableGen/listflatten.td
Log Message:
-----------
[NFC] Fix line endings for OptionStrCmp.h and .td test files (#109806)
Fix line endings for these files to Unix style.
Commit: 38371a1855dd891fdd0a6cf437e7c25b80f36dfe
https://github.com/llvm/llvm-project/commit/38371a1855dd891fdd0a6cf437e7c25b80f36dfe
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan.cpp
Log Message:
-----------
[rtsan][NFC] Make Uninitialzed state explicit (#109856)
Follow on to #109830
There should be no functional change, as enums start at 0 anyway. This
just makes the code more readable and prevents any future bugs.
Commit: 491123562a7597f8b43e317a6481c69e4d15c4e7
https://github.com/llvm/llvm-project/commit/491123562a7597f8b43e317a6481c69e4d15c4e7
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/test/Transforms/EliminateAvailableExternally/transform-to-local.ll
Log Message:
-----------
[ctx_prof] Automatically convert available external linkage to local for modules with contextual roots (#109203)
For the modules containing context roots, the way IPO happens will potentially result in imported functions that are differently specialized (even if themselves not inlined) than their originals. So we want to convert them to local rather than elide them.
Eventually we'd perform this as a ThinLTO directive.
Commit: cf9fc5e22fa51e5b3a8182e7ef408cd77064a664
https://github.com/llvm/llvm-project/commit/cf9fc5e22fa51e5b3a8182e7ef408cd77064a664
Author: c8ef <c8ef at outlook.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M cmake/Modules/CMakePolicy.cmake
Log Message:
-----------
[CMake] enable CMP0147 policy if available (#109150)
Closes #38383.
This enables parallel custom build commands, which improve compilation
time on Windows with Visual Studio.
Commit: b4130bee6bfd34d8045f02fc9f951bcb5db9d85c
https://github.com/llvm/llvm-project/commit/b4130bee6bfd34d8045f02fc9f951bcb5db9d85c
Author: Zentrik <llvm.zentrik at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
Log Message:
-----------
Fix libFuzzer not building with pthreads on Windows (#109525)
Fixes https://github.com/llvm/llvm-project/issues/106871
Commit: 538dbb97a215d4f203cb1e88455bd10a1ecd7e7d
https://github.com/llvm/llvm-project/commit/538dbb97a215d4f203cb1e88455bd10a1ecd7e7d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/splat-score-adjustment.ll
Log Message:
-----------
[SLP][NFC]Add a test with the operand reordering and bad reused values decision
Commit: b9bd8ca24e46c1fd6fa343a248936e395f103765
https://github.com/llvm/llvm-project/commit/b9bd8ca24e46c1fd6fa343a248936e395f103765
Author: Miguel A. Arroyo <miguel.arroyo at rockstargames.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/Options.td
M lld/docs/ReleaseNotes.rst
A lld/test/COFF/Inputs/include1d.yaml
M lld/test/COFF/include.test
M lld/test/COFF/include2.test
Log Message:
-----------
[LLD][COFF] Adds `/includeglob` flag (#109721)
This implements parity with the `--undefined-glob` flag on
[ELF](https://reviews.llvm.org/D63244), but for COFF.
Commit: d7dd31e41791d71ad81af9cc4e7a26b26d4cb27e
https://github.com/llvm/llvm-project/commit/d7dd31e41791d71ad81af9cc4e7a26b26d4cb27e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/splat-score-adjustment.ll
Log Message:
-----------
[SLP]Better analysis of the repeated instructions during operands reordering
When doing the repeated instructions analysis, better to make the
reordering non-profitable, if the number of unique instructions is not
power-of-2. In this case better to keep power-of-2 elements as this
allows better vectorization.
Fixes https://github.com/llvm/llvm-project/issues/109725
Commit: cace9869775a185793122f845d81a5ff46f15728
https://github.com/llvm/llvm-project/commit/cace9869775a185793122f845d81a5ff46f15728
Author: Evan Wilde <ewilde at apple.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/cmake/modules/CMakeLists.txt
M llvm/cmake/modules/LLVMConfig.cmake.in
Log Message:
-----------
Export empty vt_gen target (for standalone builds) (#109817)
Fixing the standalone builds by exporting the vt_gen target so that the
sources of the clangCodeGen target can form an explicit dependency edge
on it.
Commit: df4f828938db807fc7c4611896fe9659af482e81
https://github.com/llvm/llvm-project/commit/df4f828938db807fc7c4611896fe9659af482e81
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h
Log Message:
-----------
[lldb][NFC] Replace lldb's DWARFFormValue::ValueType with llvm's (#109853)
Commit: 5d88fd33ee03105c02130e4f130ccf87997d940e
https://github.com/llvm/llvm-project/commit/5d88fd33ee03105c02130e4f130ccf87997d940e
Author: Eric Fiselier <eric at efcs.ca>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M libcxx/utils/ci/docker-compose.yml
Log Message:
-----------
attempt to bump actions runner bot version so I can build a new image
Commit: aeb18ebbe0a1a2fbce9b432eefed46c1d90968ea
https://github.com/llvm/llvm-project/commit/aeb18ebbe0a1a2fbce9b432eefed46c1d90968ea
Author: Michael Jones <michaelrj at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M libc/src/sys/socket/linux/CMakeLists.txt
M libc/src/sys/socket/linux/recv.cpp
M libc/src/sys/socket/linux/recvfrom.cpp
M libc/src/sys/socket/linux/recvmsg.cpp
M libc/src/sys/socket/linux/socketpair.cpp
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
Log Message:
-----------
[libc] Add MSAN unpoison annotations to recv funcs (#109844)
Anywhere a struct is returned from the kernel, we need to explicitly
unpoison it for MSAN. This patch does that for the recv, recvfrom,
recvmsg, and socketpair functions.
Commit: 7bd4f1a0ed64aaf13e6acdafaaf50c4e7bf1d4dc
https://github.com/llvm/llvm-project/commit/7bd4f1a0ed64aaf13e6acdafaaf50c4e7bf1d4dc
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
Log Message:
-----------
[memprof] Use BLAKE for FrameId (#109501)
This patch uses a stronger hash function for FrameId.
Without this patch, I've observed hash collisions in fairly common
scenarios. Specifically, for a given GUID, I see three pairs of hash
collisions in the two-dimensional range 1 <= LineOffset <= 70 and
1 <= Column <= 50, which may be a bit too frequent. With the new
function, I don't see collisions at all even for a large profile.
Impact on serialization/deserialization should be as follows:
- Up to indexed memprof format Version 2, inclusive: The FrameIds
computed with the new hash function will show up as part of the
profile file. However, the deserializer only treats FrameIds as
keys (but not hash values) to retrieve Frames from the on-disk hash
table, so a change of the hash function shouldn't matter.
- For indexed memprof format Version 3, FrameIds do not show up at all
in the resulting profile file. FrameIds are only used to break ties
when we sort Frames in writeMemProfFrameArray.
Commit: ce1f01b887ea5945ec3ffb45e05e674804d5d7a7
https://github.com/llvm/llvm-project/commit/ce1f01b887ea5945ec3ffb45e05e674804d5d7a7
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/source/Symbol/UnwindPlan.cpp
Log Message:
-----------
[lldb][NFC] Add the UnwindPlan method for the header update
In 206408732bca2ef464732a39c8319d47c8a1dbea I updated the
UnwindPlan header to include a new method, but didn't add
the actual implementation. Fix that.
Commit: ab0bd344d6556634646001f720e9a0b47801a1a4
https://github.com/llvm/llvm-project/commit/ab0bd344d6556634646001f720e9a0b47801a1a4
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Log Message:
-----------
[compiler-rt] Fix #109834 for Android (#109876)
Commit: 98260a1a2786f5e639fbcf7a1f3540554f0692f0
https://github.com/llvm/llvm-project/commit/98260a1a2786f5e639fbcf7a1f3540554f0692f0
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Log Message:
-----------
[RISCV] Add reversed select testcase for canSplatOperand [nfc]
Commit: 6c7134b2667b3abbbb3f56352a0020f398994d14
https://github.com/llvm/llvm-project/commit/6c7134b2667b3abbbb3f56352a0020f398994d14
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Don't create MachineMemOperand in foldMemoryOperandImpl. (#109840)
The caller already does this after we return. I think it will overwrite
any MMO we add.
I'm the original author of this code and I'm not sure why I did it.
Commit: 1f9ca897987358053374b724444c2aa396e51032
https://github.com/llvm/llvm-project/commit/1f9ca897987358053374b724444c2aa396e51032
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Don't create insert/extract subreg during lowering. (#109754)
Create the equivalent INSERT_SUBVECTOR/EXTRACT_SUBVECTOR instead.
When we tried porting this to global isel, we noticed that subreg
operations are created early. We aren't able to do this until
instruction selection in global isel.
For SelectionDAG, it makes sense to use insert/extract_subvector as the
canonical form for these operations pre-isel. If it had come into
SelectionDAG as a insert/extract_subvector we would have kept it in that
form.
Commit: 4c4fb6ada7a168e5129a22efb4d604bb6fc60b17
https://github.com/llvm/llvm-project/commit/4c4fb6ada7a168e5129a22efb4d604bb6fc60b17
Author: yonghong-song <yhs at fb.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
A clang/test/CodeGen/bpf-attr-type-tag-atomic.c
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFMIChecking.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
A llvm/test/CodeGen/BPF/BTF/atomics.ll
A llvm/test/CodeGen/BPF/BTF/print_btf.py
A llvm/test/CodeGen/BPF/atomics_mem_order_v1.ll
A llvm/test/CodeGen/BPF/atomics_mem_order_v3.ll
A llvm/test/CodeGen/BPF/atomics_sub64_relaxed_v1.ll
A llvm/test/CodeGen/BPF/xaddd_v1.ll
Log Message:
-----------
[BPF] Do atomic_fetch_*() pattern matching with memory ordering (#107343)
Three commits in this pull request:
commit 1: implement pattern matching for memory ordering seq_cst,
acq_rel, release, acquire and monotonic. Specially, for monotonic memory
ordering (relaxed memory model), if no return value is used, locked insn
is used.
commit 2: add support to handle dwarf atomic modifier in BTF generation.
Actually atomic modifier is ignored in BTF.
commit 3: add tests for new atomic ordering support and BTF support with
_Atomic type.
I removed RFC tag as now patch sets are in reasonable states.
For atomic fetch_and_*() operations, do pattern matching with memory
ordering
seq_cst, acq_rel, release, acquire and monotonic (relaxed). For
fetch_and_*()
operations with seq_cst/acq_rel/release/acquire ordering,
atomic_fetch_*()
instructions are generated. For monotonic ordering, locked insns are
generated
if return value is not used. Otherwise, atomic_fetch_*() insns are used.
The main motivation is to resolve the kernel issue [1].
The following are memory ordering are supported:
seq_cst, acq_rel, release, acquire, relaxed
Current gcc style __sync_fetch_and_*() operations are all seq_cst.
To use explicit memory ordering, the _Atomic type is needed. The
following is
an example:
```
$ cat test.c
\#include <stdatomic.h>
void f1(_Atomic int *i) {
(void)__c11_atomic_fetch_and(i, 10, memory_order_relaxed);
}
void f2(_Atomic int *i) {
(void)__c11_atomic_fetch_and(i, 10, memory_order_acquire);
}
void f3(_Atomic int *i) {
(void)__c11_atomic_fetch_and(i, 10, memory_order_seq_cst);
}
$ cat run.sh
clang -I/home/yhs/work/bpf-next/tools/testing/selftests/bpf -O2 --target=bpf -c test.c -o test.o && llvm-objdum
p -d test.o
$ ./run.sh
test.o: file format elf64-bpf
Disassembly of section .text:
0000000000000000 <f1>:
0: b4 02 00 00 0a 00 00 00 w2 = 0xa
1: c3 21 00 00 50 00 00 00 lock *(u32 *)(r1 + 0x0) &= w2
2: 95 00 00 00 00 00 00 00 exit
0000000000000018 <f2>:
3: b4 02 00 00 0a 00 00 00 w2 = 0xa
4: c3 21 00 00 51 00 00 00 w2 = atomic_fetch_and((u32 *)(r1 + 0x0), w2)
5: 95 00 00 00 00 00 00 00 exit
0000000000000030 <f3>:
6: b4 02 00 00 0a 00 00 00 w2 = 0xa
7: c3 21 00 00 51 00 00 00 w2 = atomic_fetch_and((u32 *)(r1 + 0x0), w2)
8: 95 00 00 00 00 00 00 00 exit
```
The following is another example where return value is used:
```
$ cat test1.c
\#include <stdatomic.h>
int f1(_Atomic int *i) {
return __c11_atomic_fetch_and(i, 10, memory_order_relaxed);
}
int f2(_Atomic int *i) {
return __c11_atomic_fetch_and(i, 10, memory_order_acquire);
}
int f3(_Atomic int *i) {
return __c11_atomic_fetch_and(i, 10, memory_order_seq_cst);
}
$ cat run.sh
clang -I/home/yhs/work/bpf-next/tools/testing/selftests/bpf -O2 --target=bpf -c test1.c -o test1.o && llvm-objdump -d test1.o
$ ./run.sh
test.o: file format elf64-bpf
Disassembly of section .text:
0000000000000000 <f1>:
0: b4 00 00 00 0a 00 00 00 w0 = 0xa
1: c3 01 00 00 51 00 00 00 w0 = atomic_fetch_and((u32 *)(r1 + 0x0), w0)
2: 95 00 00 00 00 00 00 00 exit
0000000000000018 <f2>:
3: b4 00 00 00 0a 00 00 00 w0 = 0xa
4: c3 01 00 00 51 00 00 00 w0 = atomic_fetch_and((u32 *)(r1 + 0x0), w0)
5: 95 00 00 00 00 00 00 00 exit
0000000000000030 <f3>:
6: b4 00 00 00 0a 00 00 00 w0 = 0xa
7: c3 01 00 00 51 00 00 00 w0 = atomic_fetch_and((u32 *)(r1 + 0x0), w0)
8: 95 00 00 00 00 00 00 00 exit
```
You can see that for relaxed memory ordering, if return value is used,
atomic_fetch_and()
insn is used. Otherwise, if return value is not used, locked insn is
used.
Here is another example with global _Atomic variable:
```
$ cat test3.c
\#include <stdatomic.h>
_Atomic int i;
void f1(void) {
(void)__c11_atomic_fetch_and(&i, 10, memory_order_relaxed);
}
void f2(void) {
(void)__c11_atomic_fetch_and(&i, 10, memory_order_seq_cst);
}
$ cat run.sh
clang -I/home/yhs/work/bpf-next/tools/testing/selftests/bpf -O2 --target=bpf -c test3.c -o test3.o && llvm-objdump -d test3.o
$ ./run.sh
test3.o: file format elf64-bpf
Disassembly of section .text:
0000000000000000 <f1>:
0: b4 01 00 00 0a 00 00 00 w1 = 0xa
1: 18 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r2 = 0x0 ll
3: c3 12 00 00 50 00 00 00 lock *(u32 *)(r2 + 0x0) &= w1
4: 95 00 00 00 00 00 00 00 exit
0000000000000028 <f2>:
5: b4 01 00 00 0a 00 00 00 w1 = 0xa
6: 18 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r2 = 0x0 ll
8: c3 12 00 00 51 00 00 00 w1 = atomic_fetch_and((u32 *)(r2 + 0x0), w1)
9: 95 00 00 00 00 00 00 00 exit
```
Note that in the above compilations, '-g' is not used. The reason is due
to the following IR
related to _Atomic type:
```
$clang -I/home/yhs/work/bpf-next/tools/testing/selftests/bpf -O2 --target=bpf -g -S -emit-llvm test3.c
```
The related debug info for test3.c:
```
!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
!1 = distinct !DIGlobalVariable(name: "i", scope: !2, file: !3, line: 3, type: !16, isLocal: false, isDefinition: true)
...
!16 = !DIDerivedType(tag: DW_TAG_atomic_type, baseType: !17)
!17 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
```
If compiling test.c, the related debug info:
```
...
!19 = distinct !DISubprogram(name: "f1", scope: !1, file: !1, line: 3, type: !20, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !25)
!20 = !DISubroutineType(types: !21)
!21 = !{null, !22}
!22 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !23, size: 64)
!23 = !DIDerivedType(tag: DW_TAG_atomic_type, baseType: !24)
!24 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!25 = !{!26}
!26 = !DILocalVariable(name: "i", arg: 1, scope: !19, file: !1, line: 3, type: !22)
```
All the above suggests _Atomic behaves like a modifier (e.g. const,
restrict, volatile).
This seems true based on doc [1].
Without proper handling DW_TAG_atomic_type, llvm BTF generation will be
incorrect since
the current implementation assumes no existence of DW_TAG_atomic_type.
So we have
two choices here:
(1). llvm bpf backend processes DW_TAG_atomic_type but ignores it in BTF
encoding.
(2). Add another type, e.g., BTF_KIND_ATOMIC to BTF. BTF_KIND_ATOMIC
behaves as a
modifier like const/volatile/restrict.
For choice (1), llvm bpf backend should skip dwarf::DW_TAG_atomic_type
during
BTF generation whenever necessary.
For choice (2), BTF_KIND_ATOMIC will be added to BTF so llvm backend and
kernel
needs to handle that properly. The main advantage of it probably is to
maintain
this atomic type so it is also available to skeleton. But I think for
skeleton
a raw type might be good enough unless user space intends to do some
atomic
operation with that, which is a unlikely case.
So I choose choice (1) in this RFC implementation. See the commit
message of the second commit for details.
[1]
https://lore.kernel.org/bpf/7b941f53-2a05-48ec-9032-8f106face3a3@linux.dev/
[2] https://dwarfstd.org/issues/131112.1.html
---------
Commit: 4a9da96dc68d878893399210888a03117b39b802
https://github.com/llvm/llvm-project/commit/4a9da96dc68d878893399210888a03117b39b802
Author: Fangrui Song <i at maskray.me>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
A clang/test/CodeGen/inline-asm-output-variant.c
A clang/test/Misc/cc1as-output-asm-variant.c
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/lib/CodeGen/LLVMTargetMachine.cpp
Log Message:
-----------
[clang] Add cc1 --output-asm-variant= to set output syntax
2fcaa549a824efeb56e807fcf750a56bf985296b (2010) added cc1as option
`-output-asm-variant` (untested) to set the output syntax.
`clang -cc1as -filetype asm -output-asm-variant 1` allows AT&T input and
Intel output (`AssemblerDialect` is also used by non-x86 targets).
This patch renames the cc1as option (to avoid collision with -o) and
makes it available for cc1 to set output syntax. This allows different
input & output syntax:
```
echo 'asm("mov $1, %eax");' | clang -xc - -S -o - -Xclang --output-asm-variant=1
```
Note: `AsmWriterFlavor` (with a misleading name), used to initialize
MCAsmInfo::AssemblerDialect, is primarily used for assembly input, not
for output.
Therefore,
`echo 'asm("mov $1, %eax");' | clang -x c - -mllvm --x86-asm-syntax=intel -S -o -`,
which achieves a similar goal before Clang 19, was unintended.
Close #109157
Pull Request: https://github.com/llvm/llvm-project/pull/109360
Commit: 02d6aad5cc940f17904c1288dfabc3fd2d439279
https://github.com/llvm/llvm-project/commit/02d6aad5cc940f17904c1288dfabc3fd2d439279
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[MemProf] Reduce unnecessary context id computation (NFC) (#109857)
One of the memory reduction techniques was to compute node context ids
on the fly. This reduced memory at the expense of some compile time
increase.
For a large binary we were spending a lot of time invoking getContextIds
on the node during assignStackNodesPostOrder, because we were iterating
through the stack ids for a call from leaf to root (first to last node
in the parlance used in that code). However, all calls for a given entry
in the StackIdToMatchingCalls map share the same last node, so we can
borrow the approach used by similar code in updateStackNodes and compute
the context ids on the last node once, then iterate each call's stack
ids in reverse order while reusing the last node's context ids.
This reduced the thin link time by 43% for a large target. It isn't
clear why there wasn't a similar increase measured when introducing the
node context id recomputation, but the compile time was longer to start
with then.
Commit: cd53c8429efc82c8756d85c23fc347901c3c948d
https://github.com/llvm/llvm-project/commit/cd53c8429efc82c8756d85c23fc347901c3c948d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix a warning
This patch fixes:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10479:12: error:
variable 'SubRegIdx' set but not used
[-Werror,-Wunused-but-set-variable]
Commit: 96eff99e64aaffed1cb8b378ed8f3ac09786e986
https://github.com/llvm/llvm-project/commit/96eff99e64aaffed1cb8b378ed8f3ac09786e986
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/tools/llvm-reduce/deltas/ReduceDistinctMetadata.cpp
Log Message:
-----------
[llvm-reduce] Avoid repeated hash lookups (NFC) (#109747)
Commit: 9a99e559322e999240184f0159993023ffb355f1
https://github.com/llvm/llvm-project/commit/9a99e559322e999240184f0159993023ffb355f1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/tools/gold/gold-plugin.cpp
Log Message:
-----------
[gold-plugin] Avoid repeated hash lookups (NFC) (#109748)
Commit: 2f9c9ff789a08a862024dab0626b40db604572c8
https://github.com/llvm/llvm-project/commit/2f9c9ff789a08a862024dab0626b40db604572c8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/tools/llvm-extract/llvm-extract.cpp
Log Message:
-----------
[llvm-extract] Avoid repeated hash lookups (NFC) (#109749)
Commit: 4c3fccdd8831c8ef8c7191a7f68e8341c3123eb7
https://github.com/llvm/llvm-project/commit/4c3fccdd8831c8ef8c7191a7f68e8341c3123eb7
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/tools/llvm-ifs/llvm-ifs.cpp
Log Message:
-----------
[llvm-ifs] Avoid repeated map lookups (NFC) (#109750)
Commit: 3cfd0c0d36975504099034ce11f4df07c5a7eba7
https://github.com/llvm/llvm-project/commit/3cfd0c0d36975504099034ce11f4df07c5a7eba7
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2024-09-25 (Wed, 25 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
A clang/test/CodeGenOpenCL/atomic-builtins-default-to-device-scope.cl
M clang/test/Sema/scoped-atomic-ops.c
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll
M llvm/test/CodeGen/SPIRV/atomicrmw.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
M llvm/test/CodeGen/SPIRV/fence.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
A llvm/test/CodeGen/SPIRV/scoped_atomicrmw.ll
Log Message:
-----------
[SPIRV][RFC] Rework / extend support for memory scopes (#106429)
This change adds support for correctly lowering the `__scoped` Clang
builtins, and corresponding scoped LLVM instructions. These were
previously unconditionally lowered to Device scope, which is possibly incorrect.
Furthermore, the default / implicit scope is changed from Device (an
OpenCL assumption) to AllSvmDevices (aka System), since the SPIR-V BE is not
OpenCL specific / can ingest IR coming from other language front-ends. OpenCL
defaulting to Device scope is now reflected in the front-end handling of atomic
ops, which seems preferable.
Commit: 4494c54326fe33d19c14df851188f867b14ded2a
https://github.com/llvm/llvm-project/commit/4494c54326fe33d19c14df851188f867b14ded2a
Author: Ryan Mansfield <ryan_mansfield at apple.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/CommandObjectScripting.cpp
M lldb/source/Commands/Options.td
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Target/TargetProperties.td
Log Message:
-----------
[lldb] Fix typos in various help messages. (#109851)
Commit: bde2357f71dfd0ab9921d7e1a5d1ae12d8c44305
https://github.com/llvm/llvm-project/commit/bde2357f71dfd0ab9921d7e1a5d1ae12d8c44305
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/Option/OptTable.h
M llvm/unittests/Option/OptionMarshallingTest.cpp
M llvm/utils/TableGen/CMakeLists.txt
R llvm/utils/TableGen/OptParserEmitter.cpp
R llvm/utils/TableGen/OptRSTEmitter.cpp
A llvm/utils/TableGen/OptionParserEmitter.cpp
A llvm/utils/TableGen/OptionRSTEmitter.cpp
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
Log Message:
-----------
[LLVM][TableGen] Rename Option emitter files (#109216)
Rename OptXXXEmitter.cpp to OptionXXXEmitter.cpp to have a less
ambiguous
name, as `Opt` could also mean optimization.
Commit: b62075e0290b5fd626e49cb901b8bc4ac09fdd60
https://github.com/llvm/llvm-project/commit/b62075e0290b5fd626e49cb901b8bc4ac09fdd60
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.h
M llvm/test/MC/WebAssembly/type-checker-errors.s
Log Message:
-----------
[WebAssembly] Allow AsmTypeCheck detect multiple errors in function (#109705)
This allows multiple errors to be reported within a function, rather
than returning on the first error and not looking at the rest of the
function.
I think the rationale for the previous behavior was that upon
encountering the first error, the value stack was not in the correct
status anymore and the rest of the function checking was not very
meaningful. But this patch makes the instruction push the correct result
type upon its completion, so the while the possibility of previous error
affecting later instructions is not zero, I think this can be more
helpful to assembly hand-writers. This also allows us to write multiple
error test cases without creating as many functions.
This is what Wabt and Binaryen wast checker/validator do as well.
Also this makes sure we return a value (true/false) within an `if` for
each instruction, removing the need for the long `if`-`else if`-`else
if` chain and making them all just `if`s. I also added newlines between
the `if`s, which I feel is easier to read.
Commit: b15bd3fc653f061e3a69e1c42a3e5f5256aa1b50
https://github.com/llvm/llvm-project/commit/b15bd3fc653f061e3a69e1c42a3e5f5256aa1b50
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp
A flang/test/Fir/CUDA/cuda-constructor.f90
Log Message:
-----------
[flang][cuda] Add global constructor for allocators registration (#109854)
This pass creates the constructor function to call the allocator
registration and adds it to the global_ctors.
Commit: 9ef9acbd4f5f84e1bfceb677a064b724f102554e
https://github.com/llvm/llvm-project/commit/9ef9acbd4f5f84e1bfceb677a064b724f102554e
Author: Chris Apple <cja-private at pm.me>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan_flags.inc
A compiler-rt/test/rtsan/halt_on_error.cpp
Log Message:
-----------
[rtsan] Introduce halt_on_error flag (#109832)
Commit: 4a2d24e814295436d0c8f928897e2c55fe0214a6
https://github.com/llvm/llvm-project/commit/4a2d24e814295436d0c8f928897e2c55fe0214a6
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/toolchain/target_flags.gni
M llvm/utils/gn/secondary/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/tool/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
M llvm/utils/gn/secondary/clang/test/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/InstallAPI/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/sanitizer_common/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/test/hwasan/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/test/lsan/BUILD.gn
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/lld/unittests/AsLibAll/BUILD.gn
M llvm/utils/gn/secondary/lld/unittests/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGenTypes/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/BTF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-dwp/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-libtool-darwin/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-ml/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/sancov/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Instrumentation/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
Log Message:
-----------
[gn] Reformat build files
Ran:
git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format
No behavior change.
Commit: e33e087a175567e88b361fd198536314a0a1fff2
https://github.com/llvm/llvm-project/commit/e33e087a175567e88b361fd198536314a0a1fff2
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2024-09-25 (Wed, 25 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
A llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
Log Message:
-----------
[MachineSink] Update register dependency correctly (#109763)
The accumulateUsedDefed() was missing if block prologue interference
check does not pass. This would cause incorrect register dependency,
which cause incorrect sinking.
Commit: 2495130c1b5c255bbcf5ff84555026649c5fa697
https://github.com/llvm/llvm-project/commit/2495130c1b5c255bbcf5ff84555026649c5fa697
Author: beetrees <b at beetr.ee>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/builtins/fp_lib.h
M compiler-rt/test/builtins/Unit/multf3_test.c
Log Message:
-----------
[compiler-rt] Add missing carry to 128x128->256 wide multiply (#97257)
Commit: 4fc08b6cd57bda1d3e28eae283f7b20f8ce463d1
https://github.com/llvm/llvm-project/commit/4fc08b6cd57bda1d3e28eae283f7b20f8ce463d1
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-09-25 (Wed, 25 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
R llvm/test/CodeGen/AMDGPU/freeze.ll
Log Message:
-----------
Revert "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)"
This reverts commit 63b2595846b86b4e4eb9afba5e97dd64e8135c10.
(llvmorg-20-init-6782-g63b2595846b8)
A few bots have been failing on `inst-select-unmerge-values.mir`
Commit: 642bfd89f94f90bc9696a81e72333f6eb1ce5f20
https://github.com/llvm/llvm-project/commit/642bfd89f94f90bc9696a81e72333f6eb1ce5f20
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-09-25 (Wed, 25 Sep 2024)
Changed paths:
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
A compiler-rt/test/ubsan/TestCases/Integer/suppressions-builtin.cpp
M compiler-rt/test/ubsan/TestCases/Misc/builtins.cpp
Log Message:
-----------
[Clang][compiler-rt][UBSan] Improve `__ubsan_handle_invalid_builtin` (#109088)
This patch improves error message, and fixes a copy-paste
mistake in GET_REPORT_OPTIONS argument.
Address comment
https://github.com/llvm/llvm-project/pull/104741#discussion_r1764323722.
---------
Co-authored-by: Vitaly Buka <vitalybuka at google.com>
Commit: 3da5e82e31712792411945b655929a1680fb476c
https://github.com/llvm/llvm-project/commit/3da5e82e31712792411945b655929a1680fb476c
Author: duk <74797529+duk-37 at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
M llvm/test/CodeGen/NVPTX/unreachable.ll
Log Message:
-----------
[NVPTX] Fix NVPTXLowerUnreachable::isLoweredToTrap logic (#109730)
Previously, this pass would not generate traps if `NoTrapAfterNoreturn`
was set and would generate traps even if the instruction directly before
the `UnreachableInst` was `llvm.trap()`.
Fix both of these problems and add some tests.
Commit: 0a42c7c6679bcc6f7be4b3d103670197acac96a9
https://github.com/llvm/llvm-project/commit/0a42c7c6679bcc6f7be4b3d103670197acac96a9
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaLookup.cpp
A clang/test/Modules/GH109879-1.cpp
A clang/test/Modules/GH109879-2.cpp
Log Message:
-----------
[clang] fix assert in ADL finding entity in the implicit global module (#109882)
This adds to the assert the implicit global module case as in module
purview.
Fixes #109879
Commit: 7a086e1b2dc05f54afae3591614feede727601fa
https://github.com/llvm/llvm-project/commit/7a086e1b2dc05f54afae3591614feede727601fa
Author: yabinc <yabinc at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/test/CodeGen/2008-07-22-bitfield-init-after-zero-len-array.c
M clang/test/CodeGen/2008-08-07-AlignPadding1.c
M clang/test/CodeGen/2009-06-14-anonymous-union-init.c
M clang/test/CodeGen/64bit-swiftcall.c
M clang/test/CodeGen/arm-swiftcall.c
M clang/test/CodeGen/const-init.c
M clang/test/CodeGen/decl.c
M clang/test/CodeGen/designated-initializers.c
M clang/test/CodeGen/ext-int.c
M clang/test/CodeGen/flexible-array-init.c
M clang/test/CodeGen/global-init.c
M clang/test/CodeGen/init.c
A clang/test/CodeGen/linux-kernel-struct-union-initializer.c
A clang/test/CodeGen/linux-kernel-struct-union-initializer2.c
M clang/test/CodeGen/mingw-long-double.c
M clang/test/CodeGen/mms-bitfields.c
M clang/test/CodeGen/union-init2.c
M clang/test/CodeGen/windows-swiftcall.c
M clang/test/CodeGenObjC/designated-initializers.m
Log Message:
-----------
[clang][CodeGen] Zero init unspecified fields in initializers in C (#97121)
When an initializer is provided to a variable, the Linux kernel relied
on the compiler to zero-initialize unspecified fields, as clarified in
https://www.spinics.net/lists/netdev/msg1007244.html.
But clang doesn't guarantee this:
1. For a union type, if an empty initializer is given, clang only
initializes bytes for the first field, left bytes for other (larger)
fields are marked as undef. Accessing those undef bytes can lead
to undefined behaviors.
2. For a union type, if an initializer explicitly sets a field, left
bytes for other (larger) fields are marked as undef.
3. When an initializer is given, clang doesn't zero initialize padding.
So this patch makes the following change:
1. In C, when an initializer is provided for a variable, zero-initialize
undef and padding fields in the initializer.
2. Document the change in LanguageExtensions.rst.
As suggested in
https://github.com/llvm/llvm-project/issues/78034#issuecomment-2183437928,
the change isn't required by C23, but it's standards conforming to do
so.
Fixes: https://github.com/llvm/llvm-project/issues/97459
Commit: 489acb2401b51d940fcdbe965d4a5b2d39168b96
https://github.com/llvm/llvm-project/commit/489acb2401b51d940fcdbe965d4a5b2d39168b96
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
Log Message:
-----------
[NVPTX][NFC] Refactor utilities to use std::optional (#109883)
Commit: 4ca4460bae12eefe90bf69704a33bdd5b1c9f142
https://github.com/llvm/llvm-project/commit/4ca4460bae12eefe90bf69704a33bdd5b1c9f142
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
Log Message:
-----------
[hwasan] Add "-hwasan-with-frame-record" (#109620)
It should not be implied form mapping settings.
No longer disable frame records for fixed offset.
Commit: 0e43e154e9421044a564af0d75c2cb046fb3751f
https://github.com/llvm/llvm-project/commit/0e43e154e9421044a564af0d75c2cb046fb3751f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryData.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Passes/RetpolineInsertion.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp
R bolt/test/AArch64/Inputs/iplt.ld
R bolt/test/AArch64/ifunc.c
A bolt/test/AArch64/ifunc.test
A bolt/test/Inputs/ifunc.c
A bolt/test/Inputs/iplt.ld
A bolt/test/X86/ifunc.test
M bolt/test/X86/log.test
M bolt/test/perf2bolt/perf_test.test
M bolt/unittests/Core/BinaryContext.cpp
A clang-tools-extra/docs/clang-tidy/ExternalClang-TidyExamples.rst
M clang-tools-extra/docs/clang-tidy/index.rst
M clang/CMakeLists.txt
M clang/docs/LanguageExtensions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsNVPTX.def
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Frontend/MultiplexConsumer.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ProgramState.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/SValBuilder.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/SanitizerMetadata.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Frontend/Rewrite/RewriteObjC.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/IncrementalExecutor.cpp
M clang/lib/Interpreter/IncrementalParser.cpp
M clang/lib/Interpreter/IncrementalParser.h
M clang/lib/Interpreter/Interpreter.cpp
A clang/lib/Interpreter/InterpreterValuePrinter.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/CheckExprLifetime.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/StaticAnalyzer/Checkers/StackAddrEscapeChecker.cpp
M clang/lib/StaticAnalyzer/Core/ProgramState.cpp
M clang/lib/StaticAnalyzer/Core/RegionStore.cpp
M clang/lib/StaticAnalyzer/Core/SValBuilder.cpp
M clang/test/AST/ByteCode/codegen.m
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/new-delete.cpp
A clang/test/AST/ByteCode/placement-new.cpp
M clang/test/Analysis/stack-addr-ps.cpp
M clang/test/CXX/class/class.friend/p7-cxx20.cpp
M clang/test/CXX/class/class.mfct/p1-cxx20.cpp
M clang/test/CodeGen/2008-07-22-bitfield-init-after-zero-len-array.c
M clang/test/CodeGen/2008-08-07-AlignPadding1.c
M clang/test/CodeGen/2009-06-14-anonymous-union-init.c
M clang/test/CodeGen/64bit-swiftcall.c
M clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
M clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
M clang/test/CodeGen/arm-swiftcall.c
A clang/test/CodeGen/bpf-attr-type-tag-atomic.c
M clang/test/CodeGen/const-init.c
M clang/test/CodeGen/decl.c
M clang/test/CodeGen/designated-initializers.c
M clang/test/CodeGen/ext-int.c
M clang/test/CodeGen/flexible-array-init.c
M clang/test/CodeGen/global-init.c
M clang/test/CodeGen/init.c
A clang/test/CodeGen/inline-asm-output-variant.c
A clang/test/CodeGen/linux-kernel-struct-union-initializer.c
A clang/test/CodeGen/linux-kernel-struct-union-initializer2.c
M clang/test/CodeGen/mingw-long-double.c
M clang/test/CodeGen/mms-bitfields.c
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGen/union-init2.c
M clang/test/CodeGen/windows-swiftcall.c
A clang/test/CodeGenCXX/debug-info-line-if-2.cpp
M clang/test/CodeGenObjC/designated-initializers.m
A clang/test/CodeGenOpenCL/atomic-builtins-default-to-device-scope.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/Driver/relax.s
A clang/test/Misc/cc1as-output-asm-variant.c
A clang/test/Modules/GH109879-1.cpp
A clang/test/Modules/GH109879-2.cpp
M clang/test/Preprocessor/bpf-predefined-macros.c
M clang/test/Sema/riscv-asm.c
M clang/test/Sema/scoped-atomic-ops.c
M clang/test/SemaCXX/attr-gsl-owner-pointer-std.cpp
M clang/test/SemaCXX/attr-musttail.cpp
M clang/tools/CMakeLists.txt
M clang/tools/c-index-test/core_main.cpp
M clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M clang/unittests/Interpreter/CodeCompletionTest.cpp
M clang/unittests/Interpreter/InterpreterExtensionsTest.cpp
M cmake/Modules/CMakePolicy.cmake
M compiler-rt/lib/builtins/fp_lib.h
M compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp
M compiler-rt/lib/nsan/nsan.cpp
M compiler-rt/lib/nsan/nsan_flags.inc
M compiler-rt/lib/rtsan/rtsan.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.cpp
M compiler-rt/lib/rtsan/rtsan_diagnostics.h
M compiler-rt/lib/rtsan/rtsan_flags.inc
M compiler-rt/lib/rtsan/rtsan_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
M compiler-rt/lib/sanitizer_common/sanitizer_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_posix.h
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
M compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/test/asan/TestCases/Linux/preinstalled_signal.cpp
M compiler-rt/test/asan/TestCases/Posix/coverage-fork.cpp
M compiler-rt/test/asan/lit.cfg.py
M compiler-rt/test/builtins/Unit/multf3_test.c
A compiler-rt/test/nsan/fcmp.cpp
M compiler-rt/test/profile/Posix/instrprof-dlopen-norpath.test
A compiler-rt/test/rtsan/halt_on_error.cpp
M compiler-rt/test/sanitizer_common/TestCases/Linux/prctl.cpp
A compiler-rt/test/ubsan/TestCases/Integer/suppressions-builtin.cpp
M compiler-rt/test/ubsan/TestCases/Misc/builtins.cpp
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp
M flang/test/Driver/target-cpu-features.f90
A flang/test/Fir/CUDA/cuda-constructor.f90
M libc/cmake/modules/CheckCompilerFeatures.cmake
A libc/cmake/modules/compiler_features/check_float16_conversion.cpp
M libc/config/gpu/entrypoints.txt
M libc/config/gpu/headers.txt
M libc/docs/gpu/support.rst
M libc/include/llvm-libc-macros/math-function-macros.h
M libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/newhdrgen/yaml/stdlib.yaml
M libc/spec/stdc.td
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/ManipulationFunctions.h
A libc/src/__support/FPUtil/cast.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/except_value_utils.h
M libc/src/__support/FPUtil/generic/CMakeLists.txt
M libc/src/__support/FPUtil/generic/FMA.h
M libc/src/__support/FPUtil/generic/add_sub.h
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/ceilf16.cpp
M libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp2f16.cpp
M libc/src/math/generic/expf16.cpp
M libc/src/math/generic/expm1f16.cpp
M libc/src/math/generic/floorf16.cpp
M libc/src/math/generic/rintf16.cpp
M libc/src/math/generic/roundevenf16.cpp
M libc/src/math/generic/roundf16.cpp
M libc/src/math/generic/truncf16.cpp
M libc/src/stdio/gpu/CMakeLists.txt
A libc/src/stdio/gpu/rename.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/gpu/CMakeLists.txt
A libc/src/stdlib/gpu/system.cpp
A libc/src/stdlib/system.h
M libc/src/sys/socket/linux/CMakeLists.txt
M libc/src/sys/socket/linux/recv.cpp
M libc/src/sys/socket/linux/recvfrom.cpp
M libc/src/sys/socket/linux/recvmsg.cpp
M libc/src/sys/socket/linux/socketpair.cpp
M libc/test/include/CMakeLists.txt
A libc/test/include/IsSubnormalTest.h
A libc/test/include/issubnormal_test.c
A libc/test/include/issubnormal_test.cpp
A libc/test/include/issubnormalf_test.cpp
A libc/test/include/issubnormall_test.cpp
M libc/test/src/math/smoke/AddTest.h
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/DivTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/ModfTest.h
M libc/test/src/math/smoke/MulTest.h
M libc/test/src/math/smoke/NextTowardTest.h
M libc/test/src/math/smoke/SqrtTest.h
M libc/test/src/math/smoke/SubTest.h
M libc/test/src/math/smoke/exp10f16_test.cpp
M libc/test/src/math/smoke/exp2f16_test.cpp
M libc/test/src/math/smoke/expf16_test.cpp
M libc/test/src/math/smoke/expm1f16_test.cpp
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/gpu/server/rpc_server.cpp
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__memory/unique_temporary_buffer.h
M libcxx/utils/ci/docker-compose.yml
M libcxxabi/src/demangle/ItaniumDemangle.h
M libcxxabi/test/test_demangle.pass.cpp
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/Options.td
M lld/COFF/Writer.cpp
M lld/Common/DriverDispatcher.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
M lld/MachO/InputSection.cpp
M lld/docs/ReleaseNotes.rst
A lld/test/COFF/Inputs/include1d.yaml
M lld/test/COFF/include.test
M lld/test/COFF/include2.test
M lld/test/wasm/unsupported-pic-relocations.s
M lld/test/wasm/unsupported-pic-relocations64.s
M lld/wasm/Relocations.cpp
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/index.rst
A lldb/docs/resources/addinglanguagesupport.md
M lldb/docs/use/python-reference.rst
M lldb/examples/python/cmdtemplate.py
M lldb/examples/python/templates/parsed_cmd.py
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/ABI.h
M lldb/include/lldb/Target/RegisterContextUnwind.h
M lldb/include/lldb/Target/UnwindLLDB.h
M lldb/include/lldb/Utility/CompletionRequest.h
M lldb/include/lldb/Utility/Status.h
M lldb/source/Commands/CommandObjectCommands.cpp
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Commands/CommandObjectScripting.cpp
M lldb/source/Commands/Options.td
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/Options.cpp
M lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.h
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/ArmUnwindInfo.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/FuncUnwinders.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/ABI.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Target/UnwindLLDB.cpp
M lldb/source/Utility/Status.cpp
M lldb/test/API/commands/command/script/add/TestAddParsedCommand.py
M lldb/test/API/commands/command/script/add/test_commands.py
A lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegistersSVEOnly.py
M lldb/test/API/functionalities/gdb_remote_client/TestGDBRemotePlatformFile.py
A lldb/test/API/macosx/expedited-thread-pcs/Makefile
A lldb/test/API/macosx/expedited-thread-pcs/TestExpeditedThreadPCs.py
A lldb/test/API/macosx/expedited-thread-pcs/foo.c
A lldb/test/API/macosx/expedited-thread-pcs/main.cpp
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
M lldb/unittests/Utility/StatusTest.cpp
M llvm/cmake/modules/CMakeLists.txt
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CMake.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Analysis/DXILMetadataAnalysis.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/LiveInterval.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/include/llvm/Demangle/ItaniumDemangle.h
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/Option/OptTable.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
A llvm/include/llvm/SandboxIR/Utils.h
M llvm/include/llvm/Support/OptionStrCmp.h
M llvm/include/llvm/Support/raw_ostream.h
M llvm/include/llvm/TableGen/Record.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Region.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/LLVMTargetMachine.cpp
M llvm/lib/CodeGen/LiveInterval.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/StackProtector.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp
M llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h
M llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/Object/COFFObjectFile.cpp
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/Support/ModRef.cpp
M llvm/lib/Support/OptionStrCmp.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
R llvm/lib/Target/AMDGPU/AMDGPUInsertSingleUseVDST.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFMIChecking.cpp
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/DirectX/CMakeLists.txt
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
R llvm/lib/Target/DirectX/DXILMetadata.cpp
R llvm/lib/Target/DirectX/DXILMetadata.h
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Mips/Mips.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.h
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXLowerUnreachable.cpp
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.h
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/ElimAvailExtern.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/LoopConstrainer.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
M llvm/lib/Transforms/Utils/LoopVersioning.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Region.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-select.ll
A llvm/test/Analysis/CtxProfAnalysis/handle-select.ll
M llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
M llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll
M llvm/test/Analysis/ScalarEvolution/ne-overflow.ll
M llvm/test/Analysis/ScalarEvolution/predicated-exit-count.ll
M llvm/test/Analysis/ScalarEvolution/predicated-symbolic-max-backedge-taken-count.ll
M llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/Bindings/llvm-c/atomics.ll
M llvm/test/Bindings/llvm-c/debug_info_new_format.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
A llvm/test/CodeGen/AArch64/sincos-stack-slots.ll
M llvm/test/CodeGen/AArch64/sme-streaming-mode-changing-call-disable-stackslot-scavenging.ll
M llvm/test/CodeGen/AArch64/sve-bf16-converts.ll
M llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
R llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
A llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
A llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll
M llvm/test/CodeGen/AMDGPU/shrink-true16.mir
A llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/ARM/expand-pseudos.mir
M llvm/test/CodeGen/ARM/preferred-function-alignment.ll
M llvm/test/CodeGen/ARM/vbsl.ll
A llvm/test/CodeGen/BPF/BTF/atomics.ll
A llvm/test/CodeGen/BPF/BTF/print_btf.py
A llvm/test/CodeGen/BPF/atomics_mem_order_v1.ll
A llvm/test/CodeGen/BPF/atomics_mem_order_v3.ll
A llvm/test/CodeGen/BPF/atomics_sub64_relaxed_v1.ll
A llvm/test/CodeGen/BPF/xaddd_v1.ll
A llvm/test/CodeGen/DirectX/Metadata/lib-entries.ll
A llvm/test/CodeGen/DirectX/Metadata/multiple-entries-cs-error.ll
A llvm/test/CodeGen/DirectX/Metadata/target-profile-error.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags2.ll
M llvm/test/CodeGen/DirectX/strip-call-attrs.ll
M llvm/test/CodeGen/DirectX/typed_ptr.ll
M llvm/test/CodeGen/Generic/allow-check.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties-conflict.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties.mir
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
M llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
M llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/shl.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-mult.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-sdiv.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-srem.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-udiv.ll
A llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-urem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
A llvm/test/CodeGen/NVPTX/fence-sm-90.ll
M llvm/test/CodeGen/NVPTX/fence.ll
R llvm/test/CodeGen/NVPTX/intrin-nocapture.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
A llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
M llvm/test/CodeGen/PowerPC/pr59074.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
A llvm/test/CodeGen/SPARC/salvage-debug-isel.ll
M llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll
M llvm/test/CodeGen/SPIRV/atomicrmw.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_float.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_add/atomicrmw_faddfsub_half.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_double.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_float.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_shader_atomic_float_min_max/atomicrmw_fminfmax_half.ll
M llvm/test/CodeGen/SPIRV/fence.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic-ptr.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll
M llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll
A llvm/test/CodeGen/SPIRV/scoped_atomicrmw.ll
M llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
A llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
A llvm/test/CodeGen/X86/canonicalize-vars.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/extractelement-fp.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/pr38539.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/scheduler-backtracking.ll
M llvm/test/CodeGen/X86/section-stats.ll
M llvm/test/CodeGen/X86/shift-i128.ll
M llvm/test/CodeGen/X86/shift-i256.ll
M llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll
M llvm/test/DebugInfo/Generic/debug-ranges-duplication.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
A llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC.s
R llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC8.s
A llvm/test/MC/AMDGPU/amdhsa-kd-kernarg-preload.s
M llvm/test/MC/AMDGPU/flat-global.s
A llvm/test/MC/AMDGPU/gfx10_flat_instructions_err.s
M llvm/test/MC/AMDGPU/gfx10_unsupported.s
R llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
A llvm/test/MC/AMDGPU/gfx11_flat_instructions_err.s
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
A llvm/test/MC/AMDGPU/gfx12_flat_instructions_err.s
M llvm/test/MC/AMDGPU/gfx12_unsupported.s
A llvm/test/MC/AMDGPU/gfx940_unsupported.s
M llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/X86/apx/kmov.txt
M llvm/test/MC/ELF/relocation-alias.s
R llvm/test/MC/RISCV/machine-csr-names-invalid.s
M llvm/test/MC/RISCV/rv64-relax-all.s
M llvm/test/MC/WebAssembly/type-checker-errors.s
M llvm/test/MC/X86/gotpcrelx.s
M llvm/test/MC/X86/reloc-directive-elf-64.s
A llvm/test/TableGen/listflatten-error.td
A llvm/test/TableGen/listflatten.td
A llvm/test/Transforms/AggressiveInstCombine/inline-strcmp-debugloc.ll
M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
M llvm/test/Transforms/EliminateAvailableExternally/transform-to-local.ll
A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-insr.ll
M llvm/test/Transforms/InstCombine/compare-3way.ll
A llvm/test/Transforms/InstCombine/icmp-inttoptr.ll
M llvm/test/Transforms/InstCombine/phi-with-multiple-unsimplifiable-values.ll
M llvm/test/Transforms/InstCombine/scmp.ll
M llvm/test/Transforms/InstCombine/select-select.ll
M llvm/test/Transforms/InstCombine/sink_to_unreachable.ll
M llvm/test/Transforms/InstCombine/ucmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
A llvm/test/Transforms/LoopVectorize/AArch64/scalable-fp-ext-trunc-illegal-type.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/simple_early_exit.ll
M llvm/test/Transforms/MemCpyOpt/fca2memcpy.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
R llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll
R llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll
R llvm/test/Transforms/SLPVectorizer/X86/external-user-instruction-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/extract-many-users-buildvector.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractelement-insertpoint.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/extracts-with-undefs.ll
R llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll
R llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-const-undef.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-postpone.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-uses-vectorized-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-multiuse-with-insertelement.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-user-not-min.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-node-vectorized-insts.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-uses-with-deps-in-first.ll
R llvm/test/Transforms/SLPVectorizer/X86/one-element-vector.ll
R llvm/test/Transforms/SLPVectorizer/X86/peek-through-shuffle.ll
R llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll
R llvm/test/Transforms/SLPVectorizer/X86/phi-undef-input.ll
R llvm/test/Transforms/SLPVectorizer/X86/postponed_gathers.ll
R llvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll
R llvm/test/Transforms/SLPVectorizer/X86/pr31599.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduced-value-vectorized-later.ll
R llvm/test/Transforms/SLPVectorizer/X86/reduction-gather-non-scheduled-extracts.ll
R llvm/test/Transforms/SLPVectorizer/X86/reduction-modified-values.ll
R llvm/test/Transforms/SLPVectorizer/X86/reorder-clustered-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/reordered-top-scalars.ll
R llvm/test/Transforms/SLPVectorizer/X86/reordering-single-phi.ll
R llvm/test/Transforms/SLPVectorizer/X86/reused-buildvector-matching-vectorized-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/root-trunc-extract-reuse.ll
R llvm/test/Transforms/SLPVectorizer/X86/same-scalar-in-same-phi-extract.ll
R llvm/test/Transforms/SLPVectorizer/X86/scalarazied-result.ll
R llvm/test/Transforms/SLPVectorizer/X86/scalarization-overhead.ll
R llvm/test/Transforms/SLPVectorizer/X86/shrink_after_reorder2.ll
R llvm/test/Transforms/SLPVectorizer/X86/shuffle-multivector.ll
R llvm/test/Transforms/SLPVectorizer/X86/shufflebuilder-bug.ll
A llvm/test/Transforms/SLPVectorizer/X86/splat-score-adjustment.ll
R llvm/test/Transforms/SLPVectorizer/X86/stores-non-ordered.ll
R llvm/test/Transforms/SLPVectorizer/X86/unknown-entries.ll
R llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
M llvm/test/Transforms/SLPVectorizer/arith-div-undef.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-insert-mask-size.ll
M llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
M llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
M llvm/test/Transforms/SLPVectorizer/catchswitch.ll
M llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
M llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
A llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
A llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
A llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
A llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
A llvm/test/Transforms/SLPVectorizer/extractlements-gathered-first-node.ll
A llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
A llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
A llvm/test/Transforms/SLPVectorizer/gep-with-extractelement-many-users.ll
A llvm/test/Transforms/SLPVectorizer/insert-crash-index.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-const-undef.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-multiple-uses.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
A llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-node-with-multi-users.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
A llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
A llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
A llvm/test/Transforms/SLPVectorizer/one-element-vector.ll
A llvm/test/Transforms/SLPVectorizer/peek-through-shuffle.ll
A llvm/test/Transforms/SLPVectorizer/phi-node-bitwidt-op-not.ll
A llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll
A llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll
A llvm/test/Transforms/SLPVectorizer/pr31599-inseltpoison.ll
A llvm/test/Transforms/SLPVectorizer/pr31599.ll
A llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
A llvm/test/Transforms/SLPVectorizer/reduction-modified-values.ll
A llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll
A llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll
A llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
A llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
A llvm/test/Transforms/SLPVectorizer/revec-fix-109835.ll
A llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll
A llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll
A llvm/test/Transforms/SLPVectorizer/scalarazied-result.ll
A llvm/test/Transforms/SLPVectorizer/scalarization-overhead.ll
A llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
A llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll
A llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll
A llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll
A llvm/test/Transforms/SLPVectorizer/unknown-entries.ll
A llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SimplifyCFG/X86/hoist-loads-stores-with-cf.ll
M llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/speculate-derefable-load.ll
M llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
M llvm/test/lit.cfg.py
M llvm/test/tools/UpdateTestChecks/lit.local.cfg
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-basic.test
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/lit.local.cfg
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/if_target.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/if_target.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/if_target.test
A llvm/test/tools/dsymutil/X86/dwarf5-many-include-directories.test
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning-execution-mode.s
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning.s
M llvm/test/tools/llvm-readobj/COFF/arm64ec-chpe.yaml
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
M llvm/tools/gold/gold-plugin.cpp
M llvm/tools/llvm-c-test/main.c
M llvm/tools/llvm-ctxprof-util/llvm-ctxprof-util.cpp
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
M llvm/tools/llvm-extract/llvm-extract.cpp
M llvm/tools/llvm-ifs/llvm-ifs.cpp
M llvm/tools/llvm-reduce/ReducerWorkItem.cpp
M llvm/tools/llvm-reduce/TestRunner.cpp
M llvm/tools/llvm-reduce/TestRunner.h
M llvm/tools/llvm-reduce/deltas/ReduceDistinctMetadata.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/MI/LiveIntervalTest.cpp
M llvm/unittests/Option/OptionMarshallingTest.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/Support/raw_ostream_test.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/RegionTest.cpp
M llvm/utils/TableGen/CMakeLists.txt
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/CodeGenHwModes.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.h
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
R llvm/utils/TableGen/OptParserEmitter.cpp
R llvm/utils/TableGen/OptRSTEmitter.cpp
A llvm/utils/TableGen/OptionParserEmitter.cpp
A llvm/utils/TableGen/OptionRSTEmitter.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/toolchain/target_flags.gni
M llvm/utils/gn/secondary/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clang-doc/tool/BUILD.gn
M llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Interpreter/BUILD.gn
M llvm/utils/gn/secondary/clang/test/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/InstallAPI/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/sanitizer_common/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/test/hwasan/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/test/lsan/BUILD.gn
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/lld/unittests/AsLibAll/BUILD.gn
M llvm/utils/gn/secondary/lld/unittests/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/CodeGenTypes/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DebugInfo/BTF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-dwp/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-libtool-darwin/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-ml/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/sancov/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Instrumentation/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
A llvm/utils/update_mc_test_checks.py
M llvm/utils/update_test_checks.py
M mlir/include/mlir-c/BuiltinTypes.h
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Types.h
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Types.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/python/mlir/extras/types.py
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
M mlir/test/Dialect/Linalg/vectorize-convolution.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/SCF/loop-pipelining.mlir
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/python/ir/builtin_types.py
M mlir/utils/lldb-scripts/mlirDataFormatters.py
M mlir/utils/tree-sitter-mlir/grammar.js
M offload/include/OpenMP/OMPT/Callback.h
M offload/include/OpenMP/OMPT/Interface.h
M offload/plugins-nextgen/common/CMakeLists.txt
R offload/plugins-nextgen/common/OMPT/OmptCallback.cpp
M offload/src/OpenMP/OMPT/Callback.cpp
M offload/src/exports
M polly/lib/CodeGen/RuntimeDebugBuilder.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
M utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
M utils/bazel/llvm-project-overlay/libc/test/src/sys/socket/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/1b29ef2e8342...0e43e154e942
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