[all-commits] [llvm/llvm-project] d61b25: [Clang-BOLT] Drop CDSplit flag
Chao Chen via All-commits
all-commits at lists.llvm.org
Tue Sep 24 06:39:05 PDT 2024
Branch: refs/heads/users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter
Home: https://github.com/llvm/llvm-project
Commit: d61b2590f8e360695a5298311855c8649337969f
https://github.com/llvm/llvm-project/commit/d61b2590f8e360695a5298311855c8649337969f
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/CMakeLists.txt
Log Message:
-----------
[Clang-BOLT] Drop CDSplit flag
Breaks AArch64 Clang-BOLT builds:
https://github.com/llvm/llvm-project/pull/109351#issuecomment-2368584365
Commit: cce1fa39eabfca4907ff8d616618683eec1a5486
https://github.com/llvm/llvm-project/commit/cce1fa39eabfca4907ff8d616618683eec1a5486
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
Log Message:
-----------
[RISCV] Add zvfbfmin arithmetic cost model test coverage. NFC
Commit: 2cd20c255684257b86940bdda6861897f0bf3c00
https://github.com/llvm/llvm-project/commit/2cd20c255684257b86940bdda6861897f0bf3c00
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
R llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning-execution-mode.s
R llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning.s
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
Log Message:
-----------
Revert "[llvm-exegesis] Add support for pinning benchmarking process to a CPU (#85168)"
This reverts commit 6fc2451167ec991361dd0568de9a9fa2926f8da8.
This broke some more buildbots.
Commit: ce9a2c652104197a051db3788f3ec503cab3a79b
https://github.com/llvm/llvm-project/commit/ce9a2c652104197a051db3788f3ec503cab3a79b
Author: MichelleCDjunaidi <michellechrisalyn at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
A clang-tools-extra/docs/clang-tidy/ExternalClang-TidyExamples.rst
M clang-tools-extra/docs/clang-tidy/index.rst
Log Message:
-----------
[clang-tidy][doc] Add external examples (#106675)
Clang has a page where they list out external examples:
https://clang.llvm.org/docs/ExternalClangExamples.html. This mimics this page by adding some useful links specific to clang-tidy.
Commit: caf0897c9c7f6f2a142af06bff8680a23d1d4bf5
https://github.com/llvm/llvm-project/commit/caf0897c9c7f6f2a142af06bff8680a23d1d4bf5
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
Log Message:
-----------
[SPIR-V] Fix deprecation warnings after #102608 (#109447)
Follow up to fix warnings in the SPIRV backend after 2f50b280dc8e
"[DebugInfo] Enable deprecation of iterator-insertion methods (#102608)"
Commit: 40d8888f13fb54b0fe840deef23054de6544c184
https://github.com/llvm/llvm-project/commit/40d8888f13fb54b0fe840deef23054de6544c184
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/Status.h
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Utility/Status.cpp
M lldb/unittests/Utility/StatusTest.cpp
Log Message:
-----------
[lldb] Change the implementation of Status to store an llvm::Error (NFC) (#106774)
(based on a conversation I had with @labath yesterday in
https://github.com/llvm/llvm-project/pull/106442)
Most APIs that currently vend a Status would be better served by
returning llvm::Expected<> instead. If possibles APIs should be
refactored to avoid Status. The only legitimate long-term uses of Status
are objects that need to store an error for a long time (which should be
questioned as a design decision, too).
This patch makes the transition to llvm::Error easier by making the
places that cannot switch to llvm::Error explicit: They are marked with
a call to Status::clone(). Every other API can and should be refactored
to use llvm::Expected. In the end Status should only be used in very few
places.
Whenever an unchecked Error is dropped by Status it logs this to the
verbose API channel.
Implementation notes:
This patch introduces two new kinds of error_category as well as new
llvm::Error types. Here is the mapping of lldb::ErrorType to
llvm::Errors:
```
(eErrorTypeInvalid)
eErrorTypeGeneric llvm::StringError
eErrorTypePOSIX llvm::ECError
eErrorTypeMachKernel MachKernelError
eErrorTypeExpression llvm::ErrorList<ExpressionError>
eErrorTypeWin32 Win32Error
```
Relanding with built-in cloning support for llvm::ECError, and support
for initializing a Windows error with a NO_ERROR error code.
Commit: 8a9f66ca3118245f1ece5ba7ae6312889222eff9
https://github.com/llvm/llvm-project/commit/8a9f66ca3118245f1ece5ba7ae6312889222eff9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
R llvm/test/MC/RISCV/machine-csr-names-invalid.s
Log Message:
-----------
[RISCV] Remove machine-csr-names-invalid.s. NFC (#109595)
This appears to be redundant with rv32-only-csr-names.s which tests the
same registers and many more.
Commit: 27b5dc422cd3dc15b3d4410ba910d4b12272384d
https://github.com/llvm/llvm-project/commit/27b5dc422cd3dc15b3d4410ba910d4b12272384d
Author: Sean Perry <perry at ca.ibm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/CodeGen/Generic/allow-check.ll
M llvm/test/lit.cfg.py
Log Message:
-----------
Add target-byteorder for cases where endian in target triple is what matters (#107915)
I came across the subtly when setting up lit for z/OS and running it on
a Linux on Power machine. Linux on Power is little endian. This was
resulting in all of these tests being run even though the target triple
was z/OS which is big endian. The lit should really be checking if the
target is little endian not the host. The previous way didn't handle
cross compilation while running lit.
Commit: 8e8a0724c28642f49aeb313110522521d8359037
https://github.com/llvm/llvm-project/commit/8e8a0724c28642f49aeb313110522521d8359037
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
Log Message:
-----------
[llvm-debuginfod-find] Remove old parameter comment (#109637)
This patch removes a comment in llvm-debuginfod-find containing all the
cl::opt entries, which are redundant after the conversion to using
optTable. These seem to have been introduced in #108082 along with a
conversion to optTable.
Commit: 78ae2de4c692bea03d03e4c149b350543d220490
https://github.com/llvm/llvm-project/commit/78ae2de4c692bea03d03e4c149b350543d220490
Author: gonzalobg <65027571+gonzalobg at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
A llvm/test/CodeGen/NVPTX/fence-sm-90.ll
M llvm/test/CodeGen/NVPTX/fence.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
A llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
Log Message:
-----------
[NVPTX] Load/Store/Fence syncscope support (#106101)
Adds "initial" support for `syncscope` to the NVPTX backend
`load`/`store`/`fence` instructions.
Atomic Read-Modify-Write operations intentionally not supported as part
of this initial PR.
Commit: 93baa018e09bb3d4d5f4da0232321aff204caaeb
https://github.com/llvm/llvm-project/commit/93baa018e09bb3d4d5f4da0232321aff204caaeb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Log Message:
-----------
[LegalizeVectorTypes] Preserve original MemoryOperand and MemVT when widening fixed vector load to vp_load. (#109473)
Previously we were building a new memoperand with the size of the widened VT. This was causing a failure in our downstream with non-power of 2 vectorization. Alias analysis allowed rescheduling a 3 element vector load past 2 out of 3 scalar stores that overwrite what it was supposed to read.
Alias analysis considers it undefined behavior to read more than the size of the underlying object. There is an exception if the underying objects is sufficiently aligned, but that doesn't apply in my failing case.
Commit: f7d088b6168608682975759bf27b7c2ad0ae7117
https://github.com/llvm/llvm-project/commit/f7d088b6168608682975759bf27b7c2ad0ae7117
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/test/Sema/riscv-asm.c
Log Message:
-----------
[RISCV] Implement validateGlobalRegisterVariable. (#109596)
Only allow GPR registers and verify the size is the same as XLen.
This fixes the crash seen in #109588 by making it a frontend error.
gcc does accept the code so we may need to consider if we can fix the
backend. Some other targets I tried appear to have similar issues so it
might not be straightforward to fix.
Commit: 19f04e908667aade0efe2de9ae705baaf68c0ce2
https://github.com/llvm/llvm-project/commit/19f04e908667aade0efe2de9ae705baaf68c0ce2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Log Message:
-----------
[AArch64] Use MCRegister in more places. NFC
Commit: 3336d73126ae7ebaadf7c3a4d85e373eaae8cda6
https://github.com/llvm/llvm-project/commit/3336d73126ae7ebaadf7c3a4d85e373eaae8cda6
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/ABI.h
M lldb/include/lldb/Target/RegisterContextUnwind.h
M lldb/include/lldb/Target/UnwindLLDB.h
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/ArmUnwindInfo.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/FuncUnwinders.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/ABI.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
M lldb/source/Target/UnwindLLDB.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
Log Message:
-----------
[lldb][NFC] New names for the two RegisterLocation classes (#109611)
lldb has two RegisterLocation classes that do slightly different things.
UnwindPlan::Row::RegisterLocation (new: AbstractRegisterLocation) has a
description of how to find a register's value or location, not specific
to a particular stopping point. It may say that at a given offset into a
function, the caller's register has been spilled to stack memory at CFA
minus an offset. Or it may say that the caller's register is at a DWARF
exprssion.
UnwindLLDB::RegisterLocation (new: ConcreteRegisterLocation) is a
specific address where the register is currently stored, or the register
it has been copied into, or its value at this point in the current
function execution.
When lldb stops in a function, it interprets the
AbstractRegisterLocation's instructions using the register context and
stack memory, to create the ConcreteRegisterLocation at this point in
time for this stack frame.
I'm not thrilled with AbstractRegisterLocation and
ConcreteRegisterLocation, but it's better than the same name and it will
be easier to update them if someone suggests a better pair.
Commit: 62f3eae466cc6af101a9bfa21e2af4ff5c95658d
https://github.com/llvm/llvm-project/commit/62f3eae466cc6af101a9bfa21e2af4ff5c95658d
Author: Lei Huang <lei at ca.ibm.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
M clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
Log Message:
-----------
[PowerPC] Fix incorrect store alignment for __builtin_vsx_build_pair() (#108606)
Fixes #107229
Commit: df0864e761107b07e38f5503e0cbee0cebb4c5e8
https://github.com/llvm/llvm-project/commit/df0864e761107b07e38f5503e0cbee0cebb4c5e8
Author: Fangrui Song <i at maskray.me>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Move elf::symtab into Ctx
Remove the global variable `symtab` and add a member variable
(`std::unique_ptr<SymbolTable>`) to `Ctx` instead.
This is one step toward eliminating global states.
Pull Request: https://github.com/llvm/llvm-project/pull/109612
Commit: 127349fcba81646389e4b8202b35405a5fdbef47
https://github.com/llvm/llvm-project/commit/127349fcba81646389e4b8202b35405a5fdbef47
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/cmake/modules/CheckCompilerFeatures.cmake
A libc/cmake/modules/compiler_features/check_float16_conversion.cpp
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/ManipulationFunctions.h
A libc/src/__support/FPUtil/cast.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/except_value_utils.h
M libc/src/__support/FPUtil/generic/CMakeLists.txt
M libc/src/__support/FPUtil/generic/FMA.h
M libc/src/__support/FPUtil/generic/add_sub.h
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/ceilf16.cpp
M libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp2f16.cpp
M libc/src/math/generic/expf16.cpp
M libc/src/math/generic/expm1f16.cpp
M libc/src/math/generic/floorf16.cpp
M libc/src/math/generic/rintf16.cpp
M libc/src/math/generic/roundevenf16.cpp
M libc/src/math/generic/roundf16.cpp
M libc/src/math/generic/truncf16.cpp
M libc/test/src/math/smoke/AddTest.h
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/DivTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/ModfTest.h
M libc/test/src/math/smoke/MulTest.h
M libc/test/src/math/smoke/NextTowardTest.h
M libc/test/src/math/smoke/SqrtTest.h
M libc/test/src/math/smoke/SubTest.h
M libc/test/src/math/smoke/exp10f16_test.cpp
M libc/test/src/math/smoke/exp2f16_test.cpp
M libc/test/src/math/smoke/expf16_test.cpp
M libc/test/src/math/smoke/expm1f16_test.cpp
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
[libc][math] Add floating-point cast independent of compiler runtime (#105152)
Fixes build and tests with compiler-rt on x86.
Commit: 5927c6745c2a60c368d7bcb789a1f561d62fa039
https://github.com/llvm/llvm-project/commit/5927c6745c2a60c368d7bcb789a1f561d62fa039
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/test/MC/AMDGPU/gfx10_unsupported.s
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_unsupported.s
A llvm/test/MC/AMDGPU/gfx940_unsupported.s
Log Message:
-----------
[AMDGPU][MC] Instructions not to be supported in GFX940 (#109225)
Buffer_store_lds_dword, buffer_wbinvl1, and buffer_wbinvl1_vol are
obsolete in GFX940 and should not be supported.
Commit: 1693c6392299d1d4bea5b07094c1c562b7ee533f
https://github.com/llvm/llvm-project/commit/1693c6392299d1d4bea5b07094c1c562b7ee533f
Author: Xiaoyang Liu <siujoeng.lau at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libcxx/docs/Status/Cxx23Issues.csv
Log Message:
-----------
[libc++][NFC] mark LWG3723 as implemented (#109356)
This patch marks LWG3723 as implemented, with the implementation
completed in commit 87f3ff3 and released in `libc++` 17.0.
Closes #105104
Commit: 97b0d2076f53f669f27dc6d0539a3d01f28381e7
https://github.com/llvm/llvm-project/commit/97b0d2076f53f669f27dc6d0539a3d01f28381e7
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/Status.h
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Utility/Status.cpp
M lldb/unittests/Utility/StatusTest.cpp
Log Message:
-----------
Revert "[lldb] Change the implementation of Status to store an llvm::Error (NFC) (#106774)"
This reverts commit 40d8888f13fb54b0fe840deef23054de6544c184.
One last Windows failure remaining.
Commit: 1c47fa9b620d0abb280647b4f361ada43784d00e
https://github.com/llvm/llvm-project/commit/1c47fa9b620d0abb280647b4f361ada43784d00e
Author: Daniel Hernandez-Juarez <dhernandez0 at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
Log Message:
-----------
[mlir][AMDGPU] Add support for AMD f16 math library calls (#108809)
In this PR we add support for AMD f16 math library calls
(`__ocml_*_f16`)
CC: @krzysz00 @manupak
Commit: 3db0f8c895d4e814a18b754f9afbb1e03bd839a5
https://github.com/llvm/llvm-project/commit/3db0f8c895d4e814a18b754f9afbb1e03bd839a5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/reduced-value-vectorized-later.ll
Log Message:
-----------
[SLP]Update TrackedToOrig mappings after reduction vectorization
Need to update mappings in TrackedToOrig to correctly provide mapping
between updated reduced value after vectorization and its original
value, otherwise the compiler might miss this update and it may cause
compiler crash later, when it tries to find the original instruction
mapping for the updated value.
Fixes https://github.com/llvm/llvm-project/issues/109376
Commit: 6267f121f510859f8722c34a4a8c75e4d93b0300
https://github.com/llvm/llvm-project/commit/6267f121f510859f8722c34a4a8c75e4d93b0300
Author: OverMighty <its.overmighty at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/src/__support/FPUtil/dyadic_float.h
Log Message:
-----------
[libc] Fix missing LIBC_TYPES_HAS_FLOAT16 guard around DyadicFloat::generic_as() (#109697)
See Buildbot failure:
https://lab.llvm.org/buildbot/#/builders/93/builds/6872.
Commit: d1edef56e87631ca8712afe01ac560710a2334f2
https://github.com/llvm/llvm-project/commit/d1edef56e87631ca8712afe01ac560710a2334f2
Author: Sterling-Augustine <56981066+Sterling-Augustine at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/Type.h
A llvm/include/llvm/SandboxIR/Utils.h
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Functions to find vectorizor-relevant properties (#109221)
When vectorizing, the destination type and value of stores is more
relevant than the type of the instruction itself. Similarly for return
instructions. These functions provide a convenient way to do that
without special-casing them everywhere, and avoids the need for
friending any class that needs access to Value::LLVMTy to calculate it.
Open to better naming.
Commit: 8be6b108fbd35c6f50db488a0a5462eba6852cfd
https://github.com/llvm/llvm-project/commit/8be6b108fbd35c6f50db488a0a5462eba6852cfd
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsNVPTX.def
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
Log Message:
-----------
[NVPTX] Remove nvvm.bitcast.* intrinsics (#107936)
Remove the following intrinsics which correspond directly to a bitcast:
- llvm.nvvm.bitcast.f2i
- llvm.nvvm.bitcast.i2f
- llvm.nvvm.bitcast.d2ll
- llvm.nvvm.bitcast.ll2d
Commit: f76dae15862959deb62ec200e0958d532c908f30
https://github.com/llvm/llvm-project/commit/f76dae15862959deb62ec200e0958d532c908f30
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Only store single scalar array per VPValue in VPTransState (NFC)
After 8ec406757cb92 (https://github.com/llvm/llvm-project/pull/95842),
VPTransformState only stores a single scalar vector per VPValue.
Simplify the code by replacing the nested SmallVector in PerPartScalars with
a single SmallVector and rename to VPV2Scalars for clarity.
Commit: e093bb9e5a6884842402e2cca03f002b514e4411
https://github.com/llvm/llvm-project/commit/e093bb9e5a6884842402e2cca03f002b514e4411
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning-execution-mode.s
A llvm/test/tools/llvm-exegesis/X86/latency/cpu-pinning.s
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
Log Message:
-----------
Reland "[llvm-exegesis] Add support for pinning benchmarking process to a CPU (#85168)" (#109688)
This reverts commit 2cd20c255684257b86940bdda6861897f0bf3c00.
This relands commit 9886788a8a500a1b429a6db64397c849b112251c.
This was causing more buildbot failures due to getcpu not being
available with glibc <=2.29. This patch fixes that by directly making
the syscall, assuming the syscall number macro is available.
Commit: 416c3ce0138ff4039dab13ff634ee6392b9a3c7b
https://github.com/llvm/llvm-project/commit/416c3ce0138ff4039dab13ff634ee6392b9a3c7b
Author: vporpo <vporpodas at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement ConstantExpr (#109491)
This patch implements an empty sandboxir::ConstantExpr class, mirroring
llvm::ConstantExpr.
Commit: 6e6d5eae765939cc4074bdd606658e78c4a2a559
https://github.com/llvm/llvm-project/commit/6e6d5eae765939cc4074bdd606658e78c4a2a559
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
A lldb/test/API/macosx/expedited-thread-pcs/Makefile
A lldb/test/API/macosx/expedited-thread-pcs/TestExpeditedThreadPCs.py
A lldb/test/API/macosx/expedited-thread-pcs/foo.c
A lldb/test/API/macosx/expedited-thread-pcs/main.cpp
Log Message:
-----------
[lldb] Don't invalid register context after setting thread pc's (#109499)
Some gdb remote serial protocol stubs will send the thread IDs and PCs
for all threads in a process in the stop-reply packet. lldb often needs
to know the pc values for all threads while at a private stop, and that
results in <n-1> read-register packets for <n> threads, and can be a big
performance problem when this is a hot code path.
GDBRemoteRegisterContext tracks the StopID of when its values were set,
and when the thread's StopID has incremented, it marks all values it has
as Invalid, and knows to refetch them.
We have a code path that resulted in setting the PCs for all the
threads, and then `ProcessGDBRemote::CalculateThreadStopInfo` *forcing*
an invalidation of all the register contexts, forcing us to re-read the
pc values for all threads except the one that stopped.
There are times when it is valid to force an invalidation of the
regsiter cache - for instance, if the layout of the registers has
changed because the processor state is different, or we've sent a
write-all-registers packet to the inferior and we want to make sure we
stay in sync with the inferior. But there was no reason for this method
to be forcing the register context to be invalid.
I added a test when running on Darwin systems, where debugserver always
sends the thread IDs and PCs, which turns on packet logging. The test
runs against an inferior which has 4 threads; it steps over a dlopen()
call, steps in to a user function with debug info, steps-over and
steps-in across source lines with multiple function calls, and then
examines the packet log and flags it as an error if lldb asked for the
pc value of any thread at any point in the debug session.
For this program and the operations we're doing, with debugserver that
provides thread IDs and PCs, we should never ask for the value of a pc
register.
rdar://136247381
Commit: 2b892b05025b6e0ed2f211435f99838ea3bbccd8
https://github.com/llvm/llvm-project/commit/2b892b05025b6e0ed2f211435f99838ea3bbccd8
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/test/tools/UpdateTestChecks/lit.local.cfg
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-basic.test
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/lit.local.cfg
M llvm/utils/UpdateTestChecks/common.py
A llvm/utils/update_mc_test_checks.py
Log Message:
-----------
added a script to update llvm-mc test file (#107246)
Added a script to update the test file generated by llvm-mc binary. The
script accepts .s and .txt for asm and dasm.
For mc test I am targetting there is no function name which can be used
as a key, thus no clear mapping between input and output. The script
assumes the test are always line-by-line and it update the output marker
for each test line-by-line.
---------
Co-authored-by: Alexander Richardson <mail at alexrichardson.me>
Commit: 706e71076e0276747e7ae94e3f8a7f73a45e5b6e
https://github.com/llvm/llvm-project/commit/706e71076e0276747e7ae94e3f8a7f73a45e5b6e
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
R llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll
R llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll
R llvm/test/Transforms/SLPVectorizer/X86/external-user-instruction-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/extract-many-users-buildvector.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractelement-insertpoint.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/extracts-with-undefs.ll
R llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll
R llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-const-undef.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-postpone.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-uses-vectorized-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-multiuse-with-insertelement.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-user-not-min.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-node-vectorized-insts.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-uses-with-deps-in-first.ll
R llvm/test/Transforms/SLPVectorizer/X86/one-element-vector.ll
A llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
A llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
A llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
A llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
A llvm/test/Transforms/SLPVectorizer/extractlements-gathered-first-node.ll
A llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
A llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
A llvm/test/Transforms/SLPVectorizer/gep-with-extractelement-many-users.ll
A llvm/test/Transforms/SLPVectorizer/insert-crash-index.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-const-undef.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-multiple-uses.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
A llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-node-with-multi-users.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
A llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
A llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
A llvm/test/Transforms/SLPVectorizer/one-element-vector.ll
Log Message:
-----------
[SLP] Move some of X86 tests to common directory (#107587)
Some of the tests from the X86 directory can be generalized to improve
coverage for other architectures
Commit: 3138eb500c9462bcb6899088d49644adb4d90f62
https://github.com/llvm/llvm-project/commit/3138eb500c9462bcb6899088d49644adb4d90f62
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/CodeGenHwModes.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.h
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467)
Use const record pointers in TableGen/Common files.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
Commit: 74405b9d74d974523c0f9172a9b0c1cfd7320356
https://github.com/llvm/llvm-project/commit/74405b9d74d974523c0f9172a9b0c1cfd7320356
Author: vporpo <vporpodas at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
Log Message:
-----------
[SandboxIR] Implement a few Instruction member functions (#109709)
This patch implements some of the missing member functions of
sandboxir::Instruction.
Commit: 954ab83e6a8acb7a78936cfa3e2284b1eaf8b722
https://github.com/llvm/llvm-project/commit/954ab83e6a8acb7a78936cfa3e2284b1eaf8b722
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
A llvm/test/MC/AMDGPU/amdhsa-kd-kernarg-preload.s
Log Message:
-----------
[AMDGPU] Include unused preload kernarg in KD total SGPR count (#104743)
Unlike with implicitly preloaded data UserSGPRs firmware is unable to
handle cases where SGPRs for kernel arguments contain preloaded data but
not are not explicitly referenced in the kernel. We need to include
these preloaded SGPRs in the GRANULATED_WAVEFRONT_SGPR_COUNT calculation
to not clobber SGPRs in adjacent waves.
Commit: e44ecf76e049474190c33cd737642a0a066fb6b0
https://github.com/llvm/llvm-project/commit/e44ecf76e049474190c33cd737642a0a066fb6b0
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/test/CodeGen/X86/section-stats.ll
Log Message:
-----------
[llvm][ELF] Add ELF header/section header table size statistics (#109345)
Followup to #102363. This makes the `elf-object-writer.*Bytes` stats sum
up to `assembler.ObjectBytes`.
Commit: 16d11e26f36fa0de8ef6e402bb85e32bf7c7acd6
https://github.com/llvm/llvm-project/commit/16d11e26f36fa0de8ef6e402bb85e32bf7c7acd6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
M libc/docs/gpu/support.rst
M libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/newhdrgen/yaml/stdlib.yaml
M libc/spec/stdc.td
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/gpu/CMakeLists.txt
A libc/src/stdlib/gpu/system.cpp
A libc/src/stdlib/system.h
M libc/utils/gpu/server/rpc_server.cpp
Log Message:
-----------
[libc] Add GPU support for the 'system' function (#109687)
Summary:
This function can easily be implemented by forwarding it to the host
process. This shows up in a few places that we might want to test the
GPU so it should be provided. Also, I find the idea of the GPU
offloading work to the CPU via `system` very funny.
Commit: 3bbe0f90f33357c27e3195207fa35c0fb44e426c
https://github.com/llvm/llvm-project/commit/3bbe0f90f33357c27e3195207fa35c0fb44e426c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M libc/config/gpu/headers.txt
M libc/docs/gpu/support.rst
Log Message:
-----------
[libc] Add 'strings.h' header on the GPU (#109661)
Summary:
These are GNU extensions but still show up, the entrypoints were enabled
but we weren't emitting the header so they couldn't be used.
Commit: 1fae1314f1ff58f3601640c0a2c48cee3a322e5d
https://github.com/llvm/llvm-project/commit/1fae1314f1ff58f3601640c0a2c48cee3a322e5d
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lldb/include/lldb/Utility/Status.h
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Utility/Status.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestGDBRemotePlatformFile.py
M lldb/unittests/Utility/StatusTest.cpp
Log Message:
-----------
[lldb] Change the implementation of Status to store an llvm::Error (NFC) (#106774)
(based on a conversation I had with @labath yesterday in
https://github.com/llvm/llvm-project/pull/106442)
Most APIs that currently vend a Status would be better served by
returning llvm::Expected<> instead. If possibles APIs should be
refactored to avoid Status. The only legitimate long-term uses of Status
are objects that need to store an error for a long time (which should be
questioned as a design decision, too).
This patch makes the transition to llvm::Error easier by making the
places that cannot switch to llvm::Error explicit: They are marked with
a call to Status::clone(). Every other API can and should be refactored
to use llvm::Expected. In the end Status should only be used in very few
places.
Whenever an unchecked Error is dropped by Status it logs this to the
verbose API channel.
Implementation notes:
This patch introduces two new kinds of error_category as well as new
llvm::Error types. Here is the mapping of lldb::ErrorType to
llvm::Errors:
```
(eErrorTypeInvalid)
eErrorTypeGeneric llvm::StringError
eErrorTypePOSIX llvm::ECError
eErrorTypeMachKernel MachKernelError
eErrorTypeExpression llvm::ErrorList<ExpressionError>
eErrorTypeWin32 Win32Error
```
Relanding with built-in cloning support for llvm::ECError, and support
for initializing a Windows error with a NO_ERROR error code, and
modifying TestGDBRemotePlatformFile.py to support different renderings
of ENOSYS.
Commit: 9ac00b85e05d21be658d6aa0c91cbe05bb5dbde2
https://github.com/llvm/llvm-project/commit/9ac00b85e05d21be658d6aa0c91cbe05bb5dbde2
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
Log Message:
-----------
[NVPTX] deprecate nvvm.rotate.* intrinsics, cleanup funnel-shift handling (#107655)
This change deprecates the following intrinsics which can be trivially
converted to llvm funnel-shift intrinsics:
- @llvm.nvvm.rotate.b32
- @llvm.nvvm.rotate.right.b64
- @llvm.nvvm.rotate.b64
Commit: 0a5edb4de408ae0405f85c3e4c6da5233f185f63
https://github.com/llvm/llvm-project/commit/0a5edb4de408ae0405f85c3e4c6da5233f185f63
Author: Youngsuk Kim <youngsuk.kim at hpe.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryData.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Passes/RetpolineInsertion.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp
Log Message:
-----------
[bolt] Don't call llvm::raw_string_ostream::flush() (NFC)
Don't call raw_string_ostream::flush(), which is essentially a no-op.
As specified in the docs, raw_string_ostream is always unbuffered.
( 65b13610a5226b84889b923bae884ba395ad084d for further reference )
Commit: 783bac7ffb8f0d58d7381d90fcaa082eb0be1c1d
https://github.com/llvm/llvm-project/commit/783bac7ffb8f0d58d7381d90fcaa082eb0be1c1d
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
A llvm/test/Analysis/CtxProfAnalysis/handle-select.ll
Log Message:
-----------
[ctx_prof] Handle `select` and its `step` instrumentation (#109185)
The `step` instrumentation shouldn't be treated, during use, like an `increment`. The latter is treated as a BB ID. The step isn't that, it's more of a type of value profiling. We need to distinguish between the 2 when really looking for BB IDs (==increments), and handle appropriately `step`s. In particular, we need to know when to elide them because `select`s may get elided by function cloning, if the condition of the select is statically known.
Commit: c9e2c38f2c9784b668da875b7b94074a8bb416f7
https://github.com/llvm/llvm-project/commit/c9e2c38f2c9784b668da875b7b94074a8bb416f7
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC][hwasan] Convert ShadowMapping into class (#109616)
In the next patch we can switch to enum.
Commit: 300051159b5d8caef1e74193ebfb1ed1bce21c5e
https://github.com/llvm/llvm-project/commit/300051159b5d8caef1e74193ebfb1ed1bce21c5e
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M bolt/test/X86/log.test
M bolt/test/perf2bolt/perf_test.test
Log Message:
-----------
[BOLT][test] Update log.test and perf_test
Address noisy tests by:
- perf_test: bumping sampling frequency to maximum,
- log.test: matching Binary Function "main"
Commit: 8dbb739ffb0880e4f739992d07dc6ba6edca9509
https://github.com/llvm/llvm-project/commit/8dbb739ffb0880e4f739992d07dc6ba6edca9509
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC][hwasan] Use `enum class` in `ShadowMapping` (#109617)
Commit: 3734fa8c724ce2af2f69886ca97c05c6c3717c34
https://github.com/llvm/llvm-project/commit/3734fa8c724ce2af2f69886ca97c05c6c3717c34
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/DXILMetadataAnalysis.h
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Target/DirectX/CMakeLists.txt
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
R llvm/lib/Target/DirectX/DXILMetadata.cpp
R llvm/lib/Target/DirectX/DXILMetadata.h
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
A llvm/test/CodeGen/DirectX/Metadata/lib-entries.ll
A llvm/test/CodeGen/DirectX/Metadata/multiple-entries-cs-error.ll
A llvm/test/CodeGen/DirectX/Metadata/target-profile-error.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags2.ll
M llvm/test/CodeGen/DirectX/strip-call-attrs.ll
M llvm/test/CodeGen/DirectX/typed_ptr.ll
Log Message:
-----------
[DXIL] Consume Metadata Analysis information in passes (#108034)
- Changed `DXILTranslateMetadata::translateMetadata()` to consume DXIL
Metadata Analysis information. Subsumed into `DXILTranslateMetedata.cpp`
the functionality in `DXILMetadata.*` files - that are hence deleted.
- Changed `DXILPrepare` pass to consume DXIL Metadata Analysis
information.
- Renamed `ModuleMetadataInfo::ShaderStage` to
`ModuleMetadataInfo::ShaderProfile` to better convey what it represents.
- Updated `unknown` target shader stage specification in triples of a
couple of tests.
- Added new tests for additional verification of `DXILTranslateMetadata`
pass functionality.
Commit: 9d3a57633ebb8251d2575696dfe53c67d3a47d33
https://github.com/llvm/llvm-project/commit/9d3a57633ebb8251d2575696dfe53c67d3a47d33
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
Log Message:
-----------
[RISCV] Add explicit XLenVT cast to vector load/store patterns.
This seems to be needed to get the patterns to import into GISel
properly.
Unfortunately, it also adds ~400 bytes to the SelectionDAG table.
I'm hoping if we remove i32 as a legal type for GPR registers, this
will go down.
Commit: eddbd4eb081fedddd4028244418f89e4bf5ffb09
https://github.com/llvm/llvm-project/commit/eddbd4eb081fedddd4028244418f89e4bf5ffb09
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
[clang][NFC] add static for internal linkage function (#109436)
Detected by clang-tidy misc-use-internal-linkage
Commit: eca5949031c31fe5ff5ad7a5df07bbce13379108
https://github.com/llvm/llvm-project/commit/eca5949031c31fe5ff5ad7a5df07bbce13379108
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/SanitizerMetadata.cpp
Log Message:
-----------
[codegen][NFC] add static mark for internal usage variable and function (#109431)
Detect by clang-tidy misc-use-internal-linkage
Commit: 083f0fa454b618d722424a4a530b91de18a1b3c0
https://github.com/llvm/llvm-project/commit/083f0fa454b618d722424a4a530b91de18a1b3c0
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC][hwasan] Remove code duplication in ShadowMapping::init (#109618)
The goal to is to reorder this function to make
initialization in following order:
1. Defaults
2. Target specific overrides
3. Explicit copt<> overrides
Commit: 3bb92b530f27166b9037b63568534d248ff80150
https://github.com/llvm/llvm-project/commit/3bb92b530f27166b9037b63568534d248ff80150
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Region.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Region.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/RegionTest.cpp
Log Message:
-----------
[SandboxVec] Tag insts in a Region with metadata. (#109353)
For each region, we create a metadata node. Then when an instruction is
added to the Region, it gets tagged with the metadata node for that
region. In the following example, we have a Region that contains only
the `%t0` instruction.
```
define i8 @foo(i8 %v0, i8 %v1) {
%t0 = add i8 %v0, 1, !sbvec !0
%t1 = add i8 %t0, %v1
ret i8 %t1
}
!0 = distinct !{!"region"}
```
This commit also adds a function to create regions from metadata already
present in a Function.
This metadata can be used for debugging: if we dump IR before a Region
pass, the IR will contain enough info to re-create the Region and run
the pass by itself in a later invocation.
---------
Co-authored-by: Alina Sbirlea <alina.g.simion at gmail.com>
Commit: f77bbc0b34f98a6e866a72ccd8ff18bee9fa4dc8
https://github.com/llvm/llvm-project/commit/f77bbc0b34f98a6e866a72ccd8ff18bee9fa4dc8
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.h
Log Message:
-----------
[WebAssembly] Apply clang-tidy fixes on AsmParser/TypeCheck (NFC) (#109692)
Fixes are mostly one of these:
- `auto` -> `auto *` when the type is a pointer
- Function names start with a lowercase letter
- Variable names start with an uppercase letter
- No need to have an `else` after a `return`
Diff without whitespaces is easier to view.
Commit: 00629752e622814649e67d6e5ecb02bf131b537d
https://github.com/llvm/llvm-project/commit/00629752e622814649e67d6e5ecb02bf131b537d
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
Log Message:
-----------
[SLP][REVEC] Fix cost model for getGatherCost with FixedVectorType ScalarTy. (#109369)
Commit: 0673642cab6b6a9eec20d4ea4ee6bc46db47e04c
https://github.com/llvm/llvm-project/commit/0673642cab6b6a9eec20d4ea4ee6bc46db47e04c
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
Log Message:
-----------
[hwasan] Replace "-hwasan-with-ifunc" and "-hwasan-with-tls" options (#109619)
Relationship between "-hwasan-mapping-offset",
"-hwasan-with-ifunc", and "-hwasan-with-tls" can
be to hard to understand.
Now we will have "-hwasan-mapping-offset",
presense of which will imply fixed shadow.
If "-hwasan-mapping-offset-dynamic" will set one
of 3 available dynamic shadows.
As-is "-hwasan-mapping-offset" has precedence over
"-hwasan-mapping-offset-dynamic". In follow up
patches we need to use the one with last
occurrence.
Commit: af1cf699f0bf62e54288ac3a5ada6050a41a57a1
https://github.com/llvm/llvm-project/commit/af1cf699f0bf62e54288ac3a5ada6050a41a57a1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Move OrigIdx == 0 check to start of lowerEXTRACT_SUBVECTOR. NFC (#109731)
Allows us to remove a separate check of OrigIdx != 0 for the mask case.
Commit: fd11c81a80608ddd4b33b664e28b426229aabde1
https://github.com/llvm/llvm-project/commit/fd11c81a80608ddd4b33b664e28b426229aabde1
Author: A. Jiang <de34 at live.cn>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M libcxx/include/__memory/unique_temporary_buffer.h
Log Message:
-----------
[libc++] Add `_LIBCPP_NO_CFI` to `__allocate_unique_temporary_buffer` (#109682)
Follows up #100914. Addresses the issue revealed in
https://github.com/llvm/llvm-project/pull/100914#discussion_r1771647801.
Commit: 6bed79b3f00d3e2c273bc36ed350f802d76607b3
https://github.com/llvm/llvm-project/commit/6bed79b3f00d3e2c273bc36ed350f802d76607b3
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/Support/raw_ostream.h
M llvm/unittests/Support/raw_ostream_test.cpp
Log Message:
-----------
[Support] Add scaling support in `indent` (#109478)
Scaled indent is useful when indentation is always in steps of a fixed
number (the Scale) and still allow using the +/- operators to adjust
indentation.
Commit: 86c640323286f4d692a634373c71536795cd7290
https://github.com/llvm/llvm-project/commit/86c640323286f4d692a634373c71536795cd7290
Author: c8ef <c8ef at outlook.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M compiler-rt/lib/nsan/nsan.cpp
M compiler-rt/lib/nsan/nsan_flags.inc
A compiler-rt/test/nsan/fcmp.cpp
Log Message:
-----------
[compiler-rt][nsan] Add check-cmp flag (#108707)
Add check-cmp flag.
Closes #108435.
Commit: 2028687ecad01ccc135cdc03eca933d7eec24df4
https://github.com/llvm/llvm-project/commit/2028687ecad01ccc135cdc03eca933d7eec24df4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp
Log Message:
-----------
[DWARFLinkerTypeUnit] Simplify code around try_emplace (NFC) (#109670)
Without this patch, we first default-construct a value with
try_emplace and then immediately override it with a new value.
This patch inserts the final value with try_emplace and simplies the
code around it.
Commit: 3cd3202b785654b8ac6d3bcf9ee18efcdd5171b0
https://github.com/llvm/llvm-project/commit/3cd3202b785654b8ac6d3bcf9ee18efcdd5171b0
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/include/clang/Frontend/ASTUnit.h
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/tools/c-index-test/core_main.cpp
M clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
Log Message:
-----------
[Frontend] Teach LoadFromASTFile to take FileName by StringRef (NFC) (#109583)
Without this patch, several callers of LoadFromASTFile construct an
instance of std::string to be passed as FileName, only to be converted
back to StringRef when LoadFromASTFile calls ReadAST.
This patch changes the type of FileName to StringRef and updates the
callers.
Commit: 23558afaf2f82f53ada3e9b6da3f11412dd02c8f
https://github.com/llvm/llvm-project/commit/23558afaf2f82f53ada3e9b6da3f11412dd02c8f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Hoist duplicate code in lowerINSERT_SUBVECTOR. NFC (#109733)
Commit: 64e7cb266e54e689791ad499965ddb0f8a1a2262
https://github.com/llvm/llvm-project/commit/64e7cb266e54e689791ad499965ddb0f8a1a2262
Author: Kazu Hirata <kazu at google.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/lib/Frontend/Rewrite/RewriteObjC.cpp
Log Message:
-----------
[Rewrite] Use auto (NFC)
I'm planning to change the type of BlockByCopyDecls and
BlockByRefDecls to SetVector. Declaring these iterators with auto
makes it easier to migrate to the new type.
Commit: 9b5a3036adbd9eed0f377cdf06aa622b917a1699
https://github.com/llvm/llvm-project/commit/9b5a3036adbd9eed0f377cdf06aa622b917a1699
Author: David Pagan <dave.pagan at amd.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[OpenMP][Docs] Update OpenMP supported features table (#109726)
OpenMP features table: updated scope directive status from 'worked on'
to 'done' in section OpenMP 5.1 Implementation Details.
Commit: 29168e80ba6fabb96c2b45d9deb1e908e02f8a53
https://github.com/llvm/llvm-project/commit/29168e80ba6fabb96c2b45d9deb1e908e02f8a53
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/Attributes.h
M llvm/lib/IR/Attributes.cpp
Log Message:
-----------
[IR][Attribute] Add missing `const` def on `addAllocSizeParamAttr()`; NFC
Commit: f5eaadc38b8bbe547a5019b7ceb961978f36abde
https://github.com/llvm/llvm-project/commit/f5eaadc38b8bbe547a5019b7ceb961978f36abde
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M llvm/lib/Support/ModRef.cpp
M llvm/lib/Support/OptionStrCmp.cpp
Log Message:
-----------
[NFC] Fix line endings for ModRef.cpp/OptionStrCmp.cpp (#109712)
Commit: 0206181ada4b39f0324dfe977442c65c1693f0b1
https://github.com/llvm/llvm-project/commit/0206181ada4b39f0324dfe977442c65c1693f0b1
Author: Fangrui Song <i at maskray.me>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
Log Message:
-----------
[ELF] Pass Ctx & to Driver and Writer
Commit: b30b9eb7a8823c1b3bbcd1bf9452e743a17d9223
https://github.com/llvm/llvm-project/commit/b30b9eb7a8823c1b3bbcd1bf9452e743a17d9223
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/LiveInterval.h
M llvm/lib/CodeGen/LiveInterval.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
Log Message:
-----------
LiveInterval: Make verify functions return bool (#109672)
This will allow the MachineVerifier to check these properties
instead of just asserting
Commit: fa089b014b41db4ef90378c7eae35306402cfcb3
https://github.com/llvm/llvm-project/commit/fa089b014b41db4ef90378c7eae35306402cfcb3
Author: SJW <48454132+sjw36 at users.noreply.github.com>
Date: 2024-09-23 (Mon, 23 Sep 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
M mlir/test/Dialect/SCF/loop-pipelining.mlir
Log Message:
-----------
[SCF] Fixed epilogue predicates in loop pipelining (#108964)
The computed loop iteration is zero based, so only check it is less than
zero. This fixes the case when lower bound is not zero.
Commit: cde7b30268a85a3e7900a31534a97e7eb4de9236
https://github.com/llvm/llvm-project/commit/cde7b30268a85a3e7900a31534a97e7eb4de9236
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
AMDGPU: Fix missing functions in MIR tests
This function was in the IR section, but not present in the MIR
function list.
Commit: 63b2595846b86b4e4eb9afba5e97dd64e8135c10
https://github.com/llvm/llvm-project/commit/63b2595846b86b4e4eb9afba5e97dd64e8135c10
Author: sstipano <146831748+sstipano at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
A llvm/test/CodeGen/AMDGPU/freeze.ll
Log Message:
-----------
[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)
G_FREEZE was legal for <13 x S32> which caused an infinite loop in the
combiner
Commit: 2c58063435ce4717a949585bc5c32ecf98a77238
https://github.com/llvm/llvm-project/commit/2c58063435ce4717a949585bc5c32ecf98a77238
Author: Sergey Kozub <skozub at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/include/mlir-c/BuiltinTypes.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Types.h
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Types.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/python/mlir/extras/types.py
M mlir/test/IR/attribute.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/python/ir/builtin_types.py
M mlir/utils/lldb-scripts/mlirDataFormatters.py
M mlir/utils/tree-sitter-mlir/grammar.js
Log Message:
-----------
[MLIR] Add f4E2M1FN type (#108877)
This PR adds `f4E2M1FN` type to mlir.
`f4E2M1FN` type is proposed in [OpenCompute MX
Specification](https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf).
It defines a 4-bit floating point number with bit layout S1E2M1. Unlike
IEEE-754 types, there are no infinity or NaN values.
```c
f4E2M1FN
- Exponent bias: 1
- Maximum stored exponent value: 3 (binary 11)
- Maximum unbiased exponent value: 3 - 1 = 2
- Minimum stored exponent value: 1 (binary 01)
- Minimum unbiased exponent value: 1 − 1 = 0
- Has Positive and Negative zero
- Doesn't have infinity
- Doesn't have NaNs
Additional details:
- Zeros (+/-): S.00.0
- Max normal number: S.11.1 = ±2^(2) x (1 + 0.5) = ±6.0
- Min normal number: S.01.0 = ±2^(0) = ±1.0
- Min subnormal number: S.00.1 = ±2^(0) x 0.5 = ±0.5
```
Related PRs:
- [PR-95392](https://github.com/llvm/llvm-project/pull/95392) [APFloat]
Add APFloat support for FP4 data type
- [PR-105573](https://github.com/llvm/llvm-project/pull/105573) [MLIR]
Add f6E3M2FN type - was used as a template for this PR
- [PR-107999](https://github.com/llvm/llvm-project/pull/107999) [MLIR]
Add f6E2M3FN type
Commit: f6a8eb98b13ee50c67ecf4804461a23fba7398aa
https://github.com/llvm/llvm-project/commit/f6a8eb98b13ee50c67ecf4804461a23fba7398aa
Author: Jun Wang <jwang86 at yahoo.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/MC/AMDGPU/flat-global.s
A llvm/test/MC/AMDGPU/gfx10_flat_instructions_err.s
A llvm/test/MC/AMDGPU/gfx11_flat_instructions_err.s
A llvm/test/MC/AMDGPU/gfx12_flat_instructions_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt
Log Message:
-----------
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
Some flat instructions have an saddr operand. When 'null' is provided as
saddr, it may have the same encoding as another instruction. For
example, the instructions 'global_atomic_add v1, v2, null' and
'global_atomic_add v[1:2], v2, off' have the same encoding. This patch
disallows having null as saddr.
Commit: 78ff736db2313642c3d8dd74beee3bc0b21c5c2a
https://github.com/llvm/llvm-project/commit/78ff736db2313642c3d8dd74beee3bc0b21c5c2a
Author: David Green <david.green at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
Log Message:
-----------
[ARM] Fix VMOVRRD combine with non-canonical inserts. (#109639)
In some situations, in the test case here with the multiple calls being
late legalized, we can see inserts of the form:
```
b = insert a, x, 0
c = insert b, y, 1
d = insert c, z, 0
bc = bitcast d
e = extract bc, 0
r = vmovrrd e
```
The redundant insert will usually be removed, but in some cases are not
prior to PerformVMOVRRDCombine. The code was finding the first insert
from each lane (x and y), as opposed to the last (z and y).
Commit: 5ca09d617da89c4466347030e2949dc5713eabcb
https://github.com/llvm/llvm-project/commit/5ca09d617da89c4466347030e2949dc5713eabcb
Author: David Green <david.green at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/test/CodeGen/ARM/expand-pseudos.mir
M llvm/test/CodeGen/ARM/vbsl.ll
Log Message:
-----------
[ARM] Fix VBSL Pseudo kill flags. (#109629)
When expanding a VBSP pseudo into VMOV; VBSL, if the first reg was
killed in the BSP then the kill flags could be incorrect copied to the
mov (vorr) and the vbsl. Drop the kill flags.
Note that this sometimes comes up when all the operands of the VBSP are
the same, which can be optimized separately.
Commit: 1493c247b687160aa92cf13ac1c6f363870bbac0
https://github.com/llvm/llvm-project/commit/1493c247b687160aa92cf13ac1c6f363870bbac0
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
Log Message:
-----------
[ASan][test] Fix TestCases/Posix/stack-overflow.cpp on Solaris/sparcv9 (#109101)
When ASan testing is enabled on SPARC as per PR #107405, the
```
AddressSanitizer-sparc-sunos :: TestCases/Posix/stack-overflow.cpp
```
test `FAIL`s:
```
compiler-rt/test/asan/TestCases/Posix/stack-overflow.cpp:80:12: error: CHECK: expected string not found in input
// CHECK: {{stack-overflow on address 0x.* \(pc 0x.* bp 0x.* sp 0x.* T.*\)}}
^
AddressSanitizer:DEADLYSIGNAL
AddressSanitizer:DEADLYSIGNAL
=================================================================
==11358==ERROR: AddressSanitizer: SEGV on unknown address 0xff3fff90 (pc 0x000db0c0 bp 0xfeed59f8 sp 0xfeed5978 T0)
==11358==The signal is caused by a READ memory access.
AddressSanitizer:DEADLYSIGNAL
AddressSanitizer: nested bug in the same thread, aborting.
```
It turns out that `sanitizer_linux.cpp` (`GetPcSpBp`) tries to
dereference the stack pointer to get at the saved frame pointer, which
cannot work since `sp` has been invalidated by the stack overflow in the
test. The access attempt thus leads to a second `SEGV`.
Solaris `walkcontext(3C)` doesn't have that problem: in the original
OpenSolaris sources (`$SRC/lib/libc/port/gen/walkstack.c`) they used
`/proc/self/as` to avoid the fault, which is quite heavy-handed. Solaris
11.4 uses a non-faulting load instead (`load_no_fault_uint32`, which
just uses the `lduwa` insn).
This patch follows this lead, returning a `NULL` `bp` in the failure
case. Unfortunately, this leads to `SEGV`s in the depth of the unwinder,
so this patch avoids printing a stack trace in this case.
Tested on `sparcv9-sun-solaris2.11` and `sparc64-unknown-linux-gnu`.
Commit: 4ac141683c310447f0efba775dc59b2145511ac0
https://github.com/llvm/llvm-project/commit/4ac141683c310447f0efba775dc59b2145511ac0
Author: tomasz-kaminski-sonarsource <79814193+tomasz-kaminski-sonarsource at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
M clang/test/CXX/class/class.friend/p7-cxx20.cpp
M clang/test/CXX/class/class.mfct/p1-cxx20.cpp
Log Message:
-----------
[C++20][Modules] NFC Reworked handling of inline for functions defined in class (#109470)
Reworked handling of implicit inline marking for member and friend
function defined in class.
Now, we handle it in an additive manner, i.e. if such in-class functions
are inline implicitly by language rules,
we mark the as `setImplicitInline`, and perform no action otherwise.
As we never remove inline specifier, the implementation is orthogonal to
other sources of inline
(like `inline`, `constexpr`, e.t.c), and we do not need to handle them
specially.
Also included test for `constexpr`, `consteval` and global module cases.
Commit: 3907d186d627f8957627b2861cf6f879d07c93c2
https://github.com/llvm/llvm-project/commit/3907d186d627f8957627b2861cf6f879d07c93c2
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Log Message:
-----------
[sanitizer_common] Heed __ndbl_ prefix for 32-bit Linux/sparc64 inter… (#109106)
…ceptors
When ASan testing is enabled on SPARC as per PR #107405, a couple of
tests `FAIL` on Linux/sparc64:
```
AddressSanitizer-sparc-linux :: TestCases/printf-2.c
AddressSanitizer-sparc-linux :: TestCases/printf-3.c
AddressSanitizer-sparc-linux :: TestCases/printf-4.c
AddressSanitizer-sparc-linux :: TestCases/printf-5.c
SanitizerCommon-asan-sparc-Linux :: Linux/unexpected_format_specifier_test.cpp
```
It turns out the interceptors aren't used since on Linux/sparc64
`double` and `long double` are the same, and a couple of `stdio`
functions are prefixed with `__nldbl_` (no long double) accordingly.
This patch handles this.
Tested on `sparc64-unknown-linux-gnu`.
Commit: 4a264c559922a8754a0e28fbf316ba667ec19798
https://github.com/llvm/llvm-project/commit/4a264c559922a8754a0e28fbf316ba667ec19798
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
Log Message:
-----------
[sanitizer_common] Fix GetArgsAndEnv on Linux/sparc64 (#109109)
When ASan testing is enabled on SPARC as per PR #107405, the
```
AddressSanitizer-sparc-linux :: TestCases/Posix/print_cmdline.cpp
```
test `FAIL`s. Either `ASAN_OPTIONS=print_cmdline=true` yielded binary
garbage in the `Command:` output or just an empty string.
It turns out one needs to apply an offset to `__libc_stack_end` to get
at the actual `argc`/`argv`, as described in `glibc`'s
`sysdeps/sparc/sparc{32,64}/dl-machine.h` (`DL_STACK_END`).
This patch does this, fixing the test.
Tested on `sparc64-unknown-linux-gnu`.
Commit: d814006c0aedf806f2ea09660c26f51099020b2c
https://github.com/llvm/llvm-project/commit/d814006c0aedf806f2ea09660c26f51099020b2c
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/test/asan/TestCases/Posix/coverage-fork.cpp
Log Message:
-----------
[ASan][test] Fix Posix/coverage-fork.cpp on Solaris (#109626)
With ASan testing enabled on SPARC as per PR #107405, the
```
AddressSanitizer-sparc-sunos-dynamic :: TestCases/Posix/coverage-fork.cpp
```
test occasionally `FAIL`s on Solaris/sparcv9:
```
compiler-rt/test/asan/TestCases/Posix/coverage-fork.cpp:46:15: error: CHECK-DAG: expected string not found in input
// CHECK-DAG: Parent PID: [[ParentPID:[0-9]+]]
^
```
It turns out that the output for parent and child processes is
interleaved like
```
Parent PID: Child PID: 27426
27425
```
Checking with `truss` shows that the `fprintf`s are implemented as 3
separate `write`s:
```
28489: write(2, " P a r e n t P I D : ", 12) = 12
28489: write(2, " 2 8 4 8 9", 5) = 5
28489: write(2, "\n", 1) = 1
```
To avoid this, this patch switches the test to use `snprintf`/`write` to
guarantee the output is atomic.
Tested on `sparcv9-sun-solaris2.11`, `amd64-pc-solaris2.11`, and
`x86_64-pc-linux-gnu`.
Commit: debc325bb1f58025c44393408a2b5a53ef8041f9
https://github.com/llvm/llvm-project/commit/debc325bb1f58025c44393408a2b5a53ef8041f9
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
Log Message:
-----------
[MIPS] Fix failing to legalize load+call with vector of non-p2 integer (#109625)
Add a condition to check whether the vector element type is a power of 2.
Fixes #102870.
Commit: 5cd0900ef6eb97d72803bdca7180538a40431722
https://github.com/llvm/llvm-project/commit/5cd0900ef6eb97d72803bdca7180538a40431722
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
A llvm/test/Transforms/InstCombine/icmp-inttoptr.ll
Log Message:
-----------
[InstCombine] Compare `icmp inttoptr, inttoptr` values directly (#107012)
InstCombine already has some rules for `icmp ptrtoint, ptrtoint` to drop
the casts and compare the source values. This change adds the same for
the reverse case with `inttoptr`.
Commit: 3dbd929ea6af134650dd1d91baeb61a4fc1b0eb8
https://github.com/llvm/llvm-project/commit/3dbd929ea6af134650dd1d91baeb61a4fc1b0eb8
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Log Message:
-----------
[AMDGPU][NFC] Update comment referring to SIRemoveShortExecBranches pass (#109756)
That pass no longer exists, since
5df2af8b0ef33f48b1ee72bcd27bc609b898da52 has merged it into
SIPreEmitPeephole.
Commit: e4d34261f85050af340ade9a7dcd332f11b4485f
https://github.com/llvm/llvm-project/commit/e4d34261f85050af340ade9a7dcd332f11b4485f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/codegen.m
Log Message:
-----------
[clang][bytecode] Ignore CPointerToObjCPointerCasts (#109760)
Commit: 14ab6190f6d1813cc5774dec2623862e1bd6876f
https://github.com/llvm/llvm-project/commit/14ab6190f6d1813cc5774dec2623862e1bd6876f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
M llvm/test/CodeGen/X86/canonicalize-vars.ll
Log Message:
-----------
[X86] Cleanup check prefixes in FCANONICALIZE tests for better sharing
Commit: 4b964002403a9b9be934174391ff5b698691a26b
https://github.com/llvm/llvm-project/commit/4b964002403a9b9be934174391ff5b698691a26b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/AST/ByteCode/placement-new.cpp
Log Message:
-----------
[clang][bytecode] Allow placement-new in std functions pre-C++26 (#109753)
Commit: b75174d05aa033a382d4c088e96e068a774f46da
https://github.com/llvm/llvm-project/commit/b75174d05aa033a382d4c088e96e068a774f46da
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
M compiler-rt/test/sanitizer_common/TestCases/Linux/prctl.cpp
Log Message:
-----------
[compiler-rt] prctl interception update, SECCOMP_MODE_FILTER support. (#107722)
Commit: eabc8857e77c94a09624c12cc690753f68b87825
https://github.com/llvm/llvm-project/commit/eabc8857e77c94a09624c12cc690753f68b87825
Author: eddyz87 <eddyz87 at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/lib/Basic/Targets/BPF.cpp
M clang/test/Preprocessor/bpf-predefined-macros.c
Log Message:
-----------
[BPF] make __BPF_FEATURE_MAY_GOTO available for cpuv1 (#108071)
For some reason `__BPF_FEATURE_MAY_GOTO` is available for CPUs v{2,3,4}
but is not available for CPU v1. This limitation is arbitrary:
- the instruction is never produced by LLVM backend;
- on Linux Kernel side this instruction is available in kernels that
also support CPUv4.
Hence, it is more consistent to either always allow
`__BPF_FEATURE_MAY_GOTO` or only allow it for CPUv4.
Commit: 70529b24a30943d46e361d2990268499921e28a2
https://github.com/llvm/llvm-project/commit/70529b24a30943d46e361d2990268499921e28a2
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/test/MC/Disassembler/X86/apx/kmov.txt
Log Message:
-----------
[X86][APX] Do not emit {evex} prefix for memory variant (#109759)
This was mistakely changed by #109579, which doesn't match with other
EVEX decoding.
Commit: c5672e21ca2a16ff18cdaa83db11d2edb84c5e14
https://github.com/llvm/llvm-project/commit/c5672e21ca2a16ff18cdaa83db11d2edb84c5e14
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
Log Message:
-----------
[AArch64][CostModel] Reduce the cost of fadd reduction with fast flag (#108791)
fadd reduction with
1. Fast flag set
2. No of elements in input vector is power of 2 results in series of
faddp instructions. faddp instruction has latency/throughput identical
to fadd instruction and hence, we set relative cost=1 for faddp as well.
The change didn't show any regression with SPEC17-FP(C/C++),
llvm-test-suite on Neoverse-V2.
Commit: 3659aa8079e00d7bd4f2d9c68c404a93ec297200
https://github.com/llvm/llvm-project/commit/3659aa8079e00d7bd4f2d9c68c404a93ec297200
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
A llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
A llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
Log Message:
-----------
[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. (#109685)
Both SGPR->VGPR and VGPR->AGPR spilling code give a fixup to the spill
frame indices referred in debug instructions so that they can be
entirely removed. The stack argument is present at 0th index in
DBG_VALUE and at 2nd index for DBG_VALUE_LIST.
Fixes: SWDEV-484156
Commit: 30dbbdd2ea25e3ab5596e1fb0474696b242a760c
https://github.com/llvm/llvm-project/commit/30dbbdd2ea25e3ab5596e1fb0474696b242a760c
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
Log Message:
-----------
[Bazel] Fix for 127349fcba81646389e4b8202b35405a5fdbef47
Commit: cc7b24a4d125e9a81480aaaa961a2b963bbb2ea2
https://github.com/llvm/llvm-project/commit/cc7b24a4d125e9a81480aaaa961a2b963bbb2ea2
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[NFC] Fix typos in comments (#109765)
Commit: bfd8f7ee4a85ae8873db14fa6e7e31223a1df169
https://github.com/llvm/llvm-project/commit/bfd8f7ee4a85ae8873db14fa6e7e31223a1df169
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/extractelement-fp.ll
Log Message:
-----------
[X86] SimplifyDemandedVectorEltsForTargetNode - reduce vector width of FRSQRT/FRCP ymm nodes.
If we only demand the lower subvector of a FRSQRT/FRCP node, then reduce the width of the instruction.
Commit: 396f6775143ffa80b9f0e72e7250613092d88124
https://github.com/llvm/llvm-project/commit/396f6775143ffa80b9f0e72e7250613092d88124
Author: Scott Egerton <9487234+ScottEgerton at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
R llvm/lib/Target/AMDGPU/AMDGPUInsertSingleUseVDST.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
R llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
R llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[AMDGPU] Remove unused VGPRSingleUseHintInsts feature (#109769)
Commit: fc661df41a206779a9323fb9dd49038c44084d5e
https://github.com/llvm/llvm-project/commit/fc661df41a206779a9323fb9dd49038c44084d5e
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lld/COFF/Writer.cpp
Log Message:
-----------
[LLD][COFF][NFC] Use dyn_cast on section chunks (#109701)
Instead of dyn_cast_or_null, chunk pointers are never null.
Commit: f664d313cd63893d7a4a496fdf0de988323b6b09
https://github.com/llvm/llvm-project/commit/f664d313cd63893d7a4a496fdf0de988323b6b09
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/fca2memcpy.ll
Log Message:
-----------
MemCpyOpt: replace an AA query with MSSA query (NFC) (#108535)
Fix a long-standing TODO.
Commit: 040bb37195d93f75cc7ce6b83254ab5db959a085
https://github.com/llvm/llvm-project/commit/040bb37195d93f75cc7ce6b83254ab5db959a085
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/float-induction.ll
Log Message:
-----------
[VPlan] Fix incorrect argument for CreateBinOp after 06c3a7d2d764.
06c3a7d2d764 incorrectly updated CreateBinOp to pass the debug location,
which gets interpreted as FPMath node. Remove the argument.
Commit: a3cf01d58587d81b184d40091a86d6b8bf92d240
https://github.com/llvm/llvm-project/commit/a3cf01d58587d81b184d40091a86d6b8bf92d240
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/docs/index.rst
A lldb/docs/resources/addinglanguagesupport.md
Log Message:
-----------
[lldb][docs] Resurrect the information on adding a new language (#109427)
This got deleted in e078c9507c3abb4d9bb2265c366b26557880a3e3, I presume
accidentally, because it didn't have a corresponding rst file for it.
So I've brought it back and converted it into Markdown. The content
remains accurate, from what I know at least.
It's a bit "now draw the rest of the owl" but if nothing else, it gives
you a bunch of important classes to go and research as a starting point.
You can see the original content here:
https://github.com/llvm/llvm-project/blob/5d71fc5d7b5ffe2323418a09db6eddaf84d6c662/lldb/www/adding-language-support.html
Commit: d4f38f43f5402041dd36977baa459830011d6ac6
https://github.com/llvm/llvm-project/commit/d4f38f43f5402041dd36977baa459830011d6ac6
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/test/CodeGen/ARM/preferred-function-alignment.ll
Log Message:
-----------
[LLVM][ARM][CodeGen]Define branch instruction alignment for m85 and m7 (#109647)
Branch instruction alignments were not defined for cortex-m85 and
cortex-m7 which misses an optimisation opportunity. With this patch we
see performance improvements as high as 5% on some benchmarks with most
around 1%.
Commit: ea902d1b36e4e3a7d7bdd0f7bce3c460b6dd6e80
https://github.com/llvm/llvm-project/commit/ea902d1b36e4e3a7d7bdd0f7bce3c460b6dd6e80
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/IR/Type.h
M llvm/lib/IR/LLVMContext.cpp
Log Message:
-----------
[IR] Remove deprecated opaque pointer migration methods
Remove the following methods:
* Type::getNonOpaquePointerElementType()
* Type::isOpaquePointerTy()
* LLVMContext::supportsTypedPointers()
* LLVMContext::setOpaquePointers()
These were used temporarily during the opaque pointers migration,
and are no longer needed.
Commit: 3d34053af61ff45e05d230d2678eb8e95322eb14
https://github.com/llvm/llvm-project/commit/3d34053af61ff45e05d230d2678eb8e95322eb14
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/test/Driver/relax.s
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/test/MC/ELF/relocation-alias.s
M llvm/test/MC/X86/gotpcrelx.s
M llvm/test/MC/X86/reloc-directive-elf-64.s
Log Message:
-----------
[X86,MC] Add relocation R_X86_64_REX2_GOTPCRELX (#106681)
For
mov name at GOTPCREL(%rip), %reg
test %reg, name at GOTPCREL(%rip)
binop name at GOTPCREL(%rip), %reg
where binop is one of adc, add, and, cmp, or, sbb, sub, xor
instructions, add
`R_X86_64_REX2_GOTPCRELX`/`R_X86_64_CODE_4_GOTPCRELX` = 43
if the instruction starts at 4 bytes before the relocation offset. It
similar to R_X86_64_GOTPCRELX.
Linker can treat `R_X86_64_REX2_GOTPCRELX`/`R_X86_64_CODE_4_GOTPCRELX`
as `R_X86_64_GOTPCREL` or convert the above instructions to
lea name(%rip), %reg
mov $name, %reg
test $name, %reg
binop $name, %reg
if the first byte of the instruction at the relocation `offset - 4` is
`0xd5` (namely, encoded w/ REX2 prefix) when possible.
Binutils patch:
https://github.com/bminor/binutils-gdb/commit/3d5a60de52556f6a53d71d7e607c6696450ae3e4
Binutils mailthread:
https://sourceware.org/pipermail/binutils/2023-December/131462.html
ABI discussion: https://groups.google.com/g/x86-64-abi/c/KbzaNHRB6QU
Blog: https://kanrobert.github.io/rfc/All-about-APX-relocation
Commit: 6cfe6a6b3e9578be80120add7fbe19506f747196
https://github.com/llvm/llvm-project/commit/6cfe6a6b3e9578be80120add7fbe19506f747196
Author: Georgi Mirazchiyski <georgi.mirazchiyski at codeplay.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[NFC][AMDGPU] Assert no bad shift operations will happen (#108416)
The assumption in the asserts is based on the fact that no SGPR/VGPR
register Arg mask in the ISelLowering and Legalizer can equal zero. They
are implicitly set to ~0 by default (meaning non-masked) or explicitly
to a non-zero value.
The `optimizeCompareInstr` case is different from the above described.
It requires the mask to be a power-of-two because it's a special-case
optimization, hence in this case we still cannot have an invalid shift.
This commit also silences static analysis tools wrt potential bad shifts
that could result from the output of `countr_zero(Mask)`.
Commit: 5dc15ddf575978e0115b1a6edacb59f056792a80
https://github.com/llvm/llvm-project/commit/5dc15ddf575978e0115b1a6edacb59f056792a80
Author: Georgi Mirazchiyski <georgi.mirazchiyski at codeplay.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
Log Message:
-----------
[AMDGPU] Default-initialize uninitialized class member variables (#108428)
Commit: 4f8e76684f4c1e67726222c35f173ef722464a7e
https://github.com/llvm/llvm-project/commit/4f8e76684f4c1e67726222c35f173ef722464a7e
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
Log Message:
-----------
[AsmPrinter] Do not emit label instructions after the function body if the target is SPIR-V (#107013)
AsmPrinter always creates a symbol for the end of function if valid
debug info is present. However, this breaks SPIR-V target's output,
because SPIR-V specification allows label instructions only inside a
block, not after the function body (see
https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpLabel).
This PR proposes to disable emission of label instructions after the
function body if the target is SPIR-V.
This PR is a fix of the
https://github.com/llvm/llvm-project/issues/102732 issue.
Commit: 497759e872a53964a54db941f3a1ed74446c5ed4
https://github.com/llvm/llvm-project/commit/497759e872a53964a54db941f3a1ed74446c5ed4
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
A lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegistersSVEOnly.py
Log Message:
-----------
[lldb][AArch64] Create Neon subregs when XML only includes SVE (#108365)
Fixes #107864
QEMU decided that when SVE is enabled it will only tell us about SVE
registers in the XML, and not include Neon registers. On the grounds
that the Neon V registers can be read from the bottom 128 bits of a SVE
Z register (SVE's vector length is always >= 128 bits).
To support this we create sub-registers just as we do for S and D
registers of the V registers. Except this time we use part of the Z
registers.
This change also updates our fallback for registers with unknown types
that are > 128 bit. This is detailed in
https://github.com/llvm/llvm-project/issues/87471, though that covers
more than this change fixes.
We'll now treat any register of unknown type that is >= 128 bit as a
vector of bytes. So that the user gets to see something
even if the order might be wrong.
And until lldb supports vector and union types for registers, this is
also the only way we can get a value to apply the sub-reg to, to make
the V registers.
Commit: c30fa3cde755e7519f0962f581868a09da1ea130
https://github.com/llvm/llvm-project/commit/c30fa3cde755e7519f0962f581868a09da1ea130
Author: Georgi Mirazchiyski <georgi.mirazchiyski at codeplay.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU] Fix has_single_bit assertion for Mask in SIInstrInfo (#109785)
Convert the `int64_t` Mask to `uint64_t` for `llvm::has_single_bit` to
compile.
Commit: 029b9b611d8becf04f4c525ab2b70e956b4b186d
https://github.com/llvm/llvm-project/commit/029b9b611d8becf04f4c525ab2b70e956b4b186d
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/CMake.rst
Log Message:
-----------
[llvm][docs] Improve formatting of ENABLE_PROJECTS/RUNTIMES description
* Add line breaks so it's clear what should be passed to CMake.
* Make the note into an RST note block.
* Fix a couple of markdown style plain text markers.
Commit: c1826aeef353bf4bd8b181b47a0dbb1f1af93836
https://github.com/llvm/llvm-project/commit/c1826aeef353bf4bd8b181b47a0dbb1f1af93836
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir][tensor] Add new helper hooks for RelayoutOp (#109642)
Implements two helper hooks for PackOp and UnPackOP, `getAllOuterDims`
and `getTiledOuterDims`, and adds them to RelayoutOp (that both PackOp
an UnPackOp inherit from).
This improves code re-use and also clarifies the meaning of "outer dims"
and "tiled outer dims".
Commit: 3e3780ef6ab5902cd1763e28bb143e47091bd23a
https://github.com/llvm/llvm-project/commit/3e3780ef6ab5902cd1763e28bb143e47091bd23a
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-bf16-converts.ll
Log Message:
-----------
[LLVM][CodeGen][SVE] Implement nxvf32 fpround to nxvbf16. (#107420)
Commit: 8ba334bc4ad1e20c8201b85ed0a3e3b87bc47fe1
https://github.com/llvm/llvm-project/commit/8ba334bc4ad1e20c8201b85ed0a3e3b87bc47fe1
Author: Dominik Montada <dominik.montada at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties-conflict.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties.mir
M llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
Log Message:
-----------
[MIR] Allow overriding isSSA, noPhis, noVRegs in MIR input (#108546)
Allow setting the computed properties IsSSA, NoPHIs, NoVRegs for MIR
functions in MIR input. The default value is still the computed value.
If the property is set to false, the computed result is ignored. Conflicting
values (e.g. setting IsSSA where the input MIR is clearly not SSA) lead to
an error.
Closes #37787
Commit: db054a197002c4d6b2c568d7c36d86f5fccade2d
https://github.com/llvm/llvm-project/commit/db054a197002c4d6b2c568d7c36d86f5fccade2d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/test/CodeGen/AArch64/sme-streaming-mode-changing-call-disable-stackslot-scavenging.ll
Log Message:
-----------
[AArch64][SME] Fix ADDVL addressing to scavenged stackslot. (#109674)
In https://reviews.llvm.org/D159196 we avoided stackslot scavenging
when there was no FP available. But in the case where FP is available
we need to actually prefer using the FP over the BP.
This change affects more than just SME, but it should be a general
improvement, since any slot above the (address pointed to by) FP
is always closer to FP than BP, so it makes sense to always favour
using the FP to address it when the FP is available.
This also fixes the issue for SME where this is not just preferred
but required.
Commit: 3073c3c2290a6d9b12fbaefa40dd22eef6312895
https://github.com/llvm/llvm-project/commit/3073c3c2290a6d9b12fbaefa40dd22eef6312895
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
A llvm/test/CodeGen/AArch64/sincos-stack-slots.ll
Log Message:
-----------
[SDAG] Avoid creating redundant stack slots when lowering FSINCOS (#108401)
When lowering `FSINCOS` to a library call (that takes output pointers)
we can avoid creating new stack allocations if the results of the
`FSINCOS` are being stored. Instead, we can take the destination
pointers from the stores and pass those to the library call.
---
Note: As a NFC this also adds (and uses) `RTLIB::getFSINCOS()`.
Commit: 3ec5e74c0dc99095f5961a31421c7adaf2860ec8
https://github.com/llvm/llvm-project/commit/3ec5e74c0dc99095f5961a31421c7adaf2860ec8
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fix layering for 127349fcba81646389e4b8202b35405a5fdbef47
Commit: 66c8dce82e60ebd22bbe6ce7c1550ae6de057625
https://github.com/llvm/llvm-project/commit/66c8dce82e60ebd22bbe6ce7c1550ae6de057625
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/TableGen/Record.h
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
A llvm/test/TableGen/listflatten-error.td
A llvm/test/TableGen/listflatten.td
Log Message:
-----------
[TableGen] Add a !listflatten operator to TableGen (#109346)
Add a !listflatten operator that will transform an input list of type
`list<list<X>>` to `list<X>` by concatenating elements of the
constituent lists of the input argument.
Commit: 12033e550b186f3b3e4d2ca3ce9cfc3d3a3fa6e1
https://github.com/llvm/llvm-project/commit/12033e550b186f3b3e4d2ca3ce9cfc3d3a3fa6e1
Author: Bevin Hansson <59652494+bevin-hansson at users.noreply.github.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
A llvm/test/CodeGen/SPARC/salvage-debug-isel.ll
M llvm/test/CodeGen/X86/pr57673.ll
Log Message:
-----------
[ISelDAG] Salvage debug info at isel by referring to frame indices. (#109126)
We can refer to frame index locations when salvaging debug info
for certain nodes, which prevents the compiler from optimizing
out the location.
Commit: b47d1787b51f55d69ef1b4f88e72cd54af451649
https://github.com/llvm/llvm-project/commit/b47d1787b51f55d69ef1b4f88e72cd54af451649
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][vector] Refine vectorisation of tensor.extract (#109580)
This PR fixes a bug in `isLoopInvariantIdx`. It makes sure that the
following case is vectorised as `vector.gather` (as opposed to
attempting a contiguous load):
```mlir
func.func @index_from_output_column_vector_gather_load(%src: tensor<8x128xf32>) -> tensor<8x1xf32> {
%c0 = arith.constant 0 : index
%0 = tensor.empty() : tensor<8x1xf32>
%res = linalg.generic {
indexing_maps = [#map],
iterator_types = ["parallel", "parallel"]
} outs(%0 : tensor<8x1xf32>) {
^bb0(%arg1: f32):
%1 = linalg.index 0 : index
%extracted = tensor.extract %src[%1, %c0] : tensor<8x128xf32>
linalg.yield %extracted : f32
} -> tensor<8x1xf32>
return %res : tensor<8x1xf32>
}
```
Specifically, when looking for loop-invariant indices in
`tensor.extract` Ops, any `linalg.index` Op that's used in address
colcluation should only access loop dims that are == 1. In the example
above, the following does not meet that criteria:
```mlir
%1 = linalg.index 0 : index
```
Note that this PR also effectively addresses the issue fixed in #107922,
i.e. exercised by:
* `@vectorize_nd_tensor_extract_load_1d_column_vector_using_gather_load`
`getNonUnitLoopDim` introduced in #107922 is still valid though. In
fact, it is required to identify that the following case is a contiguous
load:
```mlir
func.func @index_from_output_column_vector_contiguous_load(%src: tensor<8x128xf32>) -> tensor<8x1xf32> {
%c0 = arith.constant 0 : index
%0 = tensor.empty() : tensor<8x1xf32>
%res = linalg.generic {
indexing_maps = [#map],
iterator_types = ["parallel", "parallel"]
} outs(%0 : tensor<8x1xf32>) {
^bb0(%arg1: f32):
%1 = linalg.index 0 : index
%extracted = tensor.extract %src[%c0, %1] : tensor<8x128xf32>
linalg.yield %extracted : f32
} -> tensor<8x1xf32>
return %res : tensor<8x1xf32>
}
```
Some logic is still missing to lower the above to
`vector.transfer_read`, so it is conservatively lowered to
`vector.gather` instead (see TODO in
`getTensorExtractMemoryAccessPattern`).
There's a few additional changes:
* `getNonUnitLoopDim` is simplified and renamed as
`getTrailingNonUnitLoopDimIdx`, additional comments are added (note
that the functionality didn't change);
* extra comments in a few places, variable names in comments update to
use Markdown (which is the preferred approach in MLIR).
This is a follow-on for:
* https://github.com/llvm/llvm-project/pull/107922
* https://github.com/llvm/llvm-project/pull/102321
Commit: 106e4506ce6084e10353073d8880e2f736b74981
https://github.com/llvm/llvm-project/commit/106e4506ce6084e10353073d8880e2f736b74981
Author: David Pagan <dave.pagan at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[OpenMP][Docs] Update OpenMP release notes with 'omp scope' (#109752)
Release notes: added 'omp scope' directive to "OpenMP Support" section
of "What's New in Clang"
Commit: ebbf664aa31ac51c43a345a8a3d0734c54be7c4b
https://github.com/llvm/llvm-project/commit/ebbf664aa31ac51c43a345a8a3d0734c54be7c4b
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
Log Message:
-----------
[AMDGPU] Use shared prefix in GFX12 barrier test
Commit: 57bee1e4322d34f9760563081f9c10b6850bc2bf
https://github.com/llvm/llvm-project/commit/57bee1e4322d34f9760563081f9c10b6850bc2bf
Author: Xing Guo <higuoxing+github at gmail.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
A llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC.s
R llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC8.s
Log Message:
-----------
[JITLink] Add support for R_X86_64_PC16 relocation type. (#109630)
This patch adds support for R_X86_64_PC16 relocation type and
x86_64::Delta16 edge kind. This patch also adds missing test cases for
R_X86_64_PC32, R_X86_64_PC64 relocation types.
Commit: 02a334de6690202154ef09456c581618ff290f9a
https://github.com/llvm/llvm-project/commit/02a334de6690202154ef09456c581618ff290f9a
Author: Nathan Gauër <brioche at google.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
Log Message:
-----------
[SPIR-V] Fix bad insertion for type/id MIR (#109686)
Those instructions were inserted either after the instruction using it,
or in the middle of the module.
The first directly causes an issue. The second causes a more subtle
issue: the first type the type is inserted, the emission is fine, but
the second times, the first instruction is reused, without checking its
position in the function. This can lead to the second usage dominating
the definition.
In SPIR-V, types are usually in the header, above all code definition,
but at this stage I don't think we can, so what I do instead is to emit
it in the first basic block.
This commit reduces the failed tests with expensive checks from 107 to
71.
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 441a2e1f00c7daea5ccbcb1a54b68f67d87eb09e
https://github.com/llvm/llvm-project/commit/441a2e1f00c7daea5ccbcb1a54b68f67d87eb09e
Author: Chao Chen <chao.chen at intel.com>
Date: 2024-09-24 (Tue, 24 Sep 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryData.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Passes/RetpolineInsertion.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp
M bolt/test/X86/log.test
M bolt/test/perf2bolt/perf_test.test
A clang-tools-extra/docs/clang-tidy/ExternalClang-TidyExamples.rst
M clang-tools-extra/docs/clang-tidy/index.rst
M clang/CMakeLists.txt
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsNVPTX.def
M clang/include/clang/Frontend/ASTUnit.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/SanitizerMetadata.cpp
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/Rewrite/RewriteObjC.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/ByteCode/codegen.m
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/AST/ByteCode/placement-new.cpp
M clang/test/CXX/class/class.friend/p7-cxx20.cpp
M clang/test/CXX/class/class.mfct/p1-cxx20.cpp
M clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
M clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
M clang/test/Driver/relax.s
M clang/test/Preprocessor/bpf-predefined-macros.c
M clang/test/Sema/riscv-asm.c
M clang/tools/c-index-test/core_main.cpp
M clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp
M clang/unittests/Frontend/ASTUnitTest.cpp
M compiler-rt/lib/nsan/nsan.cpp
M compiler-rt/lib/nsan/nsan_flags.inc
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
M compiler-rt/test/asan/TestCases/Posix/coverage-fork.cpp
A compiler-rt/test/nsan/fcmp.cpp
M compiler-rt/test/sanitizer_common/TestCases/Linux/prctl.cpp
M libc/cmake/modules/CheckCompilerFeatures.cmake
A libc/cmake/modules/compiler_features/check_float16_conversion.cpp
M libc/config/gpu/entrypoints.txt
M libc/config/gpu/headers.txt
M libc/docs/gpu/support.rst
M libc/include/llvm-libc-types/rpc_opcodes_t.h
M libc/newhdrgen/yaml/stdlib.yaml
M libc/spec/stdc.td
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/ManipulationFunctions.h
A libc/src/__support/FPUtil/cast.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/except_value_utils.h
M libc/src/__support/FPUtil/generic/CMakeLists.txt
M libc/src/__support/FPUtil/generic/FMA.h
M libc/src/__support/FPUtil/generic/add_sub.h
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/ceilf16.cpp
M libc/src/math/generic/exp10f16.cpp
M libc/src/math/generic/exp2f16.cpp
M libc/src/math/generic/expf16.cpp
M libc/src/math/generic/expm1f16.cpp
M libc/src/math/generic/floorf16.cpp
M libc/src/math/generic/rintf16.cpp
M libc/src/math/generic/roundevenf16.cpp
M libc/src/math/generic/roundf16.cpp
M libc/src/math/generic/truncf16.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/gpu/CMakeLists.txt
A libc/src/stdlib/gpu/system.cpp
A libc/src/stdlib/system.h
M libc/test/src/math/smoke/AddTest.h
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/DivTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/ModfTest.h
M libc/test/src/math/smoke/MulTest.h
M libc/test/src/math/smoke/NextTowardTest.h
M libc/test/src/math/smoke/SqrtTest.h
M libc/test/src/math/smoke/SubTest.h
M libc/test/src/math/smoke/exp10f16_test.cpp
M libc/test/src/math/smoke/exp2f16_test.cpp
M libc/test/src/math/smoke/expf16_test.cpp
M libc/test/src/math/smoke/expm1f16_test.cpp
M libc/utils/MPFRWrapper/CMakeLists.txt
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/gpu/server/rpc_server.cpp
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/include/__memory/unique_temporary_buffer.h
M lld/COFF/Writer.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/MarkLive.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/ScriptParser.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
M lldb/docs/index.rst
A lldb/docs/resources/addinglanguagesupport.md
M lldb/include/lldb/Symbol/UnwindPlan.h
M lldb/include/lldb/Target/ABI.h
M lldb/include/lldb/Target/RegisterContextUnwind.h
M lldb/include/lldb/Target/UnwindLLDB.h
M lldb/include/lldb/Utility/Status.h
M lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp
M lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/UnwindAssembly/x86/UnwindAssembly-x86.cpp
M lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp
M lldb/source/Symbol/ArmUnwindInfo.cpp
M lldb/source/Symbol/DWARFCallFrameInfo.cpp
M lldb/source/Symbol/FuncUnwinders.cpp
M lldb/source/Symbol/UnwindPlan.cpp
M lldb/source/Target/ABI.cpp
M lldb/source/Target/RegisterContextUnwind.cpp
M lldb/source/Target/UnwindLLDB.cpp
M lldb/source/Utility/Status.cpp
A lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegistersSVEOnly.py
M lldb/test/API/functionalities/gdb_remote_client/TestGDBRemotePlatformFile.py
A lldb/test/API/macosx/expedited-thread-pcs/Makefile
A lldb/test/API/macosx/expedited-thread-pcs/TestExpeditedThreadPCs.py
A lldb/test/API/macosx/expedited-thread-pcs/foo.c
A lldb/test/API/macosx/expedited-thread-pcs/main.cpp
M lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
M lldb/unittests/UnwindAssembly/x86/Testx86AssemblyInspectionEngine.cpp
M lldb/unittests/Utility/StatusTest.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CMake.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Analysis/DXILMetadataAnalysis.h
M llvm/include/llvm/BinaryFormat/ELFRelocs/x86_64.def
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/LiveInterval.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/LLVMContext.h
M llvm/include/llvm/IR/Type.h
M llvm/include/llvm/SandboxIR/SandboxIR.h
M llvm/include/llvm/SandboxIR/SandboxIRValues.def
M llvm/include/llvm/SandboxIR/Type.h
A llvm/include/llvm/SandboxIR/Utils.h
M llvm/include/llvm/Support/raw_ostream.h
M llvm/include/llvm/TableGen/Record.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Region.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/DXILMetadataAnalysis.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/LiveInterval.cpp
M llvm/lib/CodeGen/LiveIntervals.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerTypeUnit.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/SandboxIR/SandboxIR.cpp
M llvm/lib/Support/ModRef.cpp
M llvm/lib/Support/OptionStrCmp.cpp
M llvm/lib/TableGen/Record.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
R llvm/lib/Target/AMDGPU/AMDGPUInsertSingleUseVDST.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/DirectX/CMakeLists.txt
M llvm/lib/Target/DirectX/DXContainerGlobals.cpp
R llvm/lib/Target/DirectX/DXILMetadata.cpp
R llvm/lib/Target/DirectX/DXILMetadata.h
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVRegularizer.cpp
M llvm/lib/Target/SPIRV/SPIRVStripConvergentIntrinsics.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.h
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Region.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
A llvm/test/Analysis/CtxProfAnalysis/handle-select.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
A llvm/test/CodeGen/AArch64/sincos-stack-slots.ll
M llvm/test/CodeGen/AArch64/sme-streaming-mode-changing-call-disable-stackslot-scavenging.ll
M llvm/test/CodeGen/AArch64/sve-bf16-converts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
A llvm/test/CodeGen/AMDGPU/amdhsa-kernarg-preload-num-sgprs.ll
M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
A llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
R llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
A llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
A llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
M llvm/test/CodeGen/ARM/expand-pseudos.mir
M llvm/test/CodeGen/ARM/preferred-function-alignment.ll
M llvm/test/CodeGen/ARM/vbsl.ll
A llvm/test/CodeGen/DirectX/Metadata/lib-entries.ll
A llvm/test/CodeGen/DirectX/Metadata/multiple-entries-cs-error.ll
A llvm/test/CodeGen/DirectX/Metadata/target-profile-error.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags.ll
M llvm/test/CodeGen/DirectX/legalize-module-flags2.ll
M llvm/test/CodeGen/DirectX/strip-call-attrs.ll
M llvm/test/CodeGen/DirectX/typed_ptr.ll
M llvm/test/CodeGen/Generic/allow-check.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties-conflict.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties.mir
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/Mips/cconv/illegal-vectors.ll
A llvm/test/CodeGen/NVPTX/fence-sm-90.ll
M llvm/test/CodeGen/NVPTX/fence.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
A llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/rotate.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
A llvm/test/CodeGen/SPARC/salvage-debug-isel.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-compilation-unit.ll
M llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
M llvm/test/CodeGen/X86/canonicalize-vars-f16-type.ll
M llvm/test/CodeGen/X86/canonicalize-vars.ll
M llvm/test/CodeGen/X86/extractelement-fp.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/section-stats.ll
M llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir
A llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC.s
R llvm/test/ExecutionEngine/JITLink/x86-64/ELF_R_X86_64_PC8.s
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
A llvm/test/MC/AMDGPU/amdhsa-kd-kernarg-preload.s
M llvm/test/MC/AMDGPU/flat-global.s
A llvm/test/MC/AMDGPU/gfx10_flat_instructions_err.s
M llvm/test/MC/AMDGPU/gfx10_unsupported.s
R llvm/test/MC/AMDGPU/gfx1150_asm_sopp.s
A llvm/test/MC/AMDGPU/gfx11_flat_instructions_err.s
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
A llvm/test/MC/AMDGPU/gfx12_flat_instructions_err.s
M llvm/test/MC/AMDGPU/gfx12_unsupported.s
A llvm/test/MC/AMDGPU/gfx940_unsupported.s
M llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx10_flat.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt
M llvm/test/MC/Disassembler/X86/apx/kmov.txt
M llvm/test/MC/ELF/relocation-alias.s
R llvm/test/MC/RISCV/machine-csr-names-invalid.s
M llvm/test/MC/X86/gotpcrelx.s
M llvm/test/MC/X86/reloc-directive-elf-64.s
A llvm/test/TableGen/listflatten-error.td
A llvm/test/TableGen/listflatten.td
A llvm/test/Transforms/InstCombine/icmp-inttoptr.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/MemCpyOpt/fca2memcpy.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/revec-getGatherCost.ll
R llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll
R llvm/test/Transforms/SLPVectorizer/X86/extended-vectorized-gathered-inst.ll
R llvm/test/Transforms/SLPVectorizer/X86/external-user-instruction-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/extract-many-users-buildvector.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractelement-insertpoint.ll
R llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll
R llvm/test/Transforms/SLPVectorizer/X86/extracts-with-undefs.ll
R llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll
R llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-const-undef.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
R llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-postpone.ll
R llvm/test/Transforms/SLPVectorizer/X86/insertelement-uses-vectorized-index.ll
R llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll
R llvm/test/Transforms/SLPVectorizer/X86/jumbled_store_crash.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-multiuse-with-insertelement.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
R llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-user-not-min.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-node-vectorized-insts.ll
R llvm/test/Transforms/SLPVectorizer/X86/multi-uses-with-deps-in-first.ll
R llvm/test/Transforms/SLPVectorizer/X86/one-element-vector.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduced-value-vectorized-later.ll
A llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
A llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
A llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
A llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
A llvm/test/Transforms/SLPVectorizer/extractlements-gathered-first-node.ll
A llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
A llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
A llvm/test/Transforms/SLPVectorizer/gep-with-extractelement-many-users.ll
A llvm/test/Transforms/SLPVectorizer/insert-crash-index.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-const-undef.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
A llvm/test/Transforms/SLPVectorizer/insert-element-multiple-uses.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
A llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
A llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
A llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-node-with-multi-users.ll
A llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
A llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
A llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
A llvm/test/Transforms/SLPVectorizer/one-element-vector.ll
M llvm/test/lit.cfg.py
M llvm/test/tools/UpdateTestChecks/lit.local.cfg
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-basic.test
A llvm/test/tools/UpdateTestChecks/update_mc_test_checks/lit.local.cfg
M llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/unittests/SandboxIR/SandboxIRTest.cpp
M llvm/unittests/Support/raw_ostream_test.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/RegionTest.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/Common/CodeGenHwModes.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.h
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
A llvm/utils/update_mc_test_checks.py
M mlir/include/mlir-c/BuiltinTypes.h
M mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Types.h
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/CAPI/IR/BuiltinTypes.cpp
M mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopPipelining.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Types.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/python/mlir/extras/types.py
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
M mlir/test/Dialect/SCF/loop-pipelining.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/python/ir/builtin_types.py
M mlir/utils/lldb-scripts/mlirDataFormatters.py
M mlir/utils/tree-sitter-mlir/grammar.js
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/chencha3/xegpu/update_xegpu_tdesc_attr_and_gather_scatter
Compare: https://github.com/llvm/llvm-project/compare/ff92bcefdd1c...441a2e1f00c7
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list