[all-commits] [llvm/llvm-project] db054a: [AArch64][SME] Fix ADDVL addressing to scavenged s...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: db054a197002c4d6b2c568d7c36d86f5fccade2d
      https://github.com/llvm/llvm-project/commit/db054a197002c4d6b2c568d7c36d86f5fccade2d
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-09-24 (Tue, 24 Sep 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/test/CodeGen/AArch64/sme-streaming-mode-changing-call-disable-stackslot-scavenging.ll

  Log Message:
  -----------
  [AArch64][SME] Fix ADDVL addressing to scavenged stackslot. (#109674)

In https://reviews.llvm.org/D159196 we avoided stackslot scavenging
when there was no FP available. But in the case where FP is available
we need to actually prefer using the FP over the BP.

This change affects more than just SME, but it should be a general
improvement, since any slot above the (address pointed to by) FP
is always closer to FP than BP, so it makes sense to always favour
using the FP to address it when the FP is available.

This also fixes the issue for SME where this is not just preferred
but required.



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