[all-commits] [llvm/llvm-project] 497759: [lldb][AArch64] Create Neon subregs when XML only ...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 497759e872a53964a54db941f3a1ed74446c5ed4
      https://github.com/llvm/llvm-project/commit/497759e872a53964a54db941f3a1ed74446c5ed4
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2024-09-24 (Tue, 24 Sep 2024)

  Changed paths:
    M lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
    M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
    A lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegistersSVEOnly.py

  Log Message:
  -----------
  [lldb][AArch64] Create Neon subregs when XML only includes SVE (#108365)

Fixes #107864

QEMU decided that when SVE is enabled it will only tell us about SVE
registers in the XML, and not include Neon registers. On the grounds
that the Neon V registers can be read from the bottom 128 bits of a SVE
Z register (SVE's vector length is always >= 128 bits).

To support this we create sub-registers just as we do for S and D
registers of the V registers. Except this time we use part of the Z
registers.

This change also updates our fallback for registers with unknown types
that are > 128 bit. This is detailed in
https://github.com/llvm/llvm-project/issues/87471, though that covers
more than this change fixes.

We'll now treat any register of unknown type that is >= 128 bit as a
vector of bytes. So that the user gets to see something
even if the order might be wrong.

And until lldb supports vector and union types for registers, this is
also the only way we can get a value to apply the sub-reg to, to make
the V registers.



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