[all-commits] [llvm/llvm-project] 9d3a57: [RISCV] Add explicit XLenVT cast to vector load/st...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d3a57633ebb8251d2575696dfe53c67d3a47d33
      https://github.com/llvm/llvm-project/commit/9d3a57633ebb8251d2575696dfe53c67d3a47d33
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-23 (Mon, 23 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

  Log Message:
  -----------
  [RISCV] Add explicit XLenVT cast to vector load/store patterns.

This seems to be needed to get the patterns to import into GISel
properly.

Unfortunately, it also adds ~400 bytes to the SelectionDAG table.
I'm hoping if we remove i32 as a legal type for GPR registers, this
will go down.



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