[all-commits] [llvm/llvm-project] b0dc7b: [AArch64][GlobalISel] Prefer to use Vector Truncat...

chuongg3 via All-commits all-commits at lists.llvm.org
Mon Sep 23 05:53:00 PDT 2024


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b0dc7b5b8617e188a926cbe06918fedab2fd5df9
      https://github.com/llvm/llvm-project/commit/b0dc7b5b8617e188a926cbe06918fedab2fd5df9
  Author: chuongg3 <chuong.goh at arm.com>
  Date:   2024-09-23 (Mon, 23 Sep 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AArch64/bswap.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
    M llvm/test/CodeGen/AArch64/fptoi.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/shift.ll
    M llvm/test/CodeGen/AArch64/shufflevector.ll
    M llvm/test/CodeGen/AArch64/xtn.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Prefer to use Vector Truncate (#105692)

Tries to combine scalarised truncates into vector truncate operations

EXAMPLE:
`%a(i32), %b(i32) = G_UNMERGE %src(<2 x i32>)`
`%T_a(i16) = G_TRUNC %a(i32)`
`%T_b(i16) = G_TRUNC %b(i32)`
`%Imp(i16) = G_IMPLICIT_DEF(i16)`
`%dst(v8i16) = G_MERGE_VALUES %T_a(i16), %T_b(i16), %Imp(i16),
%Imp(i16)`

===>
`%Imp(<2 x i32>) = G_IMPLICIT_DEF(<2 x i32>)`
`%Mid(<4 x s16>) = G_CONCAT_VECTORS %src(<2 x i32>), %Imp(<2 x i32>)`
`%dst(<4 x s16>) = G_TRUNC %Mid(<4 x s16>)`



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