[all-commits] [llvm/llvm-project] 3e0a76: [Codegen][LegalizeIntegerTypes] Improve shift thro...

[futog via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e0a76b1fd10d2f5f36d34a91b525c1d29685185
      https://github.com/llvm/llvm-project/commit/3e0a76b1fd10d2f5f36d34a91b525c1d29685185
  Author: futog <54807384+futog at users.noreply.github.com>
  Date:   2024-09-23 (Mon, 23 Sep 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/shl.ll
    M llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
    M llvm/test/CodeGen/PowerPC/pr59074.ll
    M llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/PowerPC/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
    M llvm/test/CodeGen/X86/pr38539.ll
    M llvm/test/CodeGen/X86/scheduler-backtracking.ll
    M llvm/test/CodeGen/X86/shift-i128.ll
    M llvm/test/CodeGen/X86/shift-i256.ll
    M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/X86/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
    M llvm/test/CodeGen/X86/widen-load-of-small-alloca.ll

  Log Message:
  -----------
  [Codegen][LegalizeIntegerTypes] Improve shift through stack (#96151)

Minor improvement on cc39c3b17fb2598e20ca0854f9fe6d69169d85c7.

Use an aligned stack slot to store the shifted value.
Use the native register width as shifting unit, so the load of the
shift result is aligned.

If the shift amount is a multiple of the native register width, there is
no need to do a follow-up shift after the load. I added new tests for
these cases.

Co-authored-by: Gergely Futo <gergely.futo at hightec-rt.com>



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