[all-commits] [llvm/llvm-project] c8fbd5: [llvm] use 64-bit types for result of getDwarfRegN...

[William G Hatch via All-commits]

  Branch: refs/heads/users/willghatch/width-changes-for-ptx-encoding
  Home:   https://github.com/llvm/llvm-project
  Commit: c8fbd5830e63d9f6defed936c769ba27ea8cf261
      https://github.com/llvm/llvm-project/commit/c8fbd5830e63d9f6defed936c769ba27ea8cf261
  Author: William G Hatch <william at hatch.uno>
  Date:   2024-09-20 (Fri, 20 Sep 2024)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
    M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h
    M llvm/lib/MC/MCRegisterInfo.cpp
    M llvm/lib/Target/Lanai/LanaiRegisterInfo.h

  Log Message:
  -----------
  [llvm] use 64-bit types for result of getDwarfRegNum (NFC)

The register encoding used by NVPTX and cuda-gdb basically use strings encoded as numbers.  They are always within 64-bits, but typically outside of 32-bits, since they often need at least 5 characters.

This patch changes the signature of MCRegisterInfo::getDwarfRegNum and some related data structures to use 64-bit numbers to accommodate encodings like this.

Additionally, the MCRegisterInfo::getDwarfRegNum is marked as virtual, so that targets with peculiar dwarf register mapping schemes (such as NVPTX) can override its behavior.



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