[all-commits] [llvm/llvm-project] 02a1d3: [AArch64] Extend and rewrite load zero and load un...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02a1d311bde4a90cffa661215c81f9fef1bc7967
      https://github.com/llvm/llvm-project/commit/02a1d311bde4a90cffa661215c81f9fef1bc7967
  Author: David Green <david.green at arm.com>
  Date:   2024-09-19 (Thu, 19 Sep 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
    M llvm/test/CodeGen/AArch64/extbinopload.ll
    M llvm/test/CodeGen/AArch64/load-insert-undef.ll
    M llvm/test/CodeGen/AArch64/load-insert-zero.ll
    M llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
    M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll

  Log Message:
  -----------
  [AArch64] Extend and rewrite load zero and load undef patterns (#108185)

The ldr instructions implicitly zero any upper lanes, so we can use them
for insert(zerovec, load, 0) patterns. Likewise insert(undef, load, 0)
or scalar_to_reg can reuse the scalar loads as the top bits are undef.

This patch makes sure there are patterns for each type and for each of
the normal, unaligned, roW and roX addressing modes.



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