[all-commits] [llvm/llvm-project] 8e4909: [RISCV] Remove unnecessary vand.vi from vXi1 and n...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8e4909aa198d8beaf32ee0abc59a06e2e54dc3bd
      https://github.com/llvm/llvm-project/commit/8e4909aa198d8beaf32ee0abc59a06e2e54dc3bd
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-09-18 (Wed, 18 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

  Log Message:
  -----------
  [RISCV] Remove unnecessary vand.vi from vXi1 and nvXvi1 VECTOR_REVERSE codegen. (#109071)

Use a setne with 0 instead of a trunc. We know we zero extended the node
so we can get by with a non-zero check only. The truncate lowering
doesn't know that we zero extended so has to mask the lsb.

I don't think DAG combine sees the trunc before we lower it to RISCVISD
nodes so we don't get a chance to use computeKnownBits to remove the
AND.



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