[all-commits] [llvm/llvm-project] edac1b: [RISCV] Promote bf16 ops to f32 with zvfbfmin (#10...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: edac1b2d63b27f83bef99f9d51f1230ea2f3f0fa
      https://github.com/llvm/llvm-project/commit/edac1b2d63b27f83bef99f9d51f1230ea2f3f0fa
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-09-18 (Wed, 18 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

  Log Message:
  -----------
  [RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

For f16 with zvfhmin, we promote most ops and VP ops to f32. This does
the same for bf16 with zvfbfmin, so the two fp types should now be in
sync.

There are a few places in the custom lowering where we need to check for
a LMUL 8 f16/bf16 vector that can't be promoted and must be split, this
extracts that out into isPromotedOpNeedingSplit.

In a follow up NFC we can deduplicate the code that sets up the
promotions.



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