[all-commits] [llvm/llvm-project] 09fc17: [RISCV] Add scheduling model for Syntacore SCR7 (#...

[Anton Sidorenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 09fc1781807b46e2c6a92e744e70a1ffb530c3ad
      https://github.com/llvm/llvm-project/commit/09fc1781807b46e2c6a92e744e70a1ffb530c3ad
  Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
  Date:   2024-09-17 (Tue, 17 Sep 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR7-ALU.s
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR7-FPALU_D.s
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR7-FPALU_S.s
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR7-LSU.s

  Log Message:
  -----------
  [RISCV] Add scheduling model for Syntacore SCR7 (#108814)

Syntacore SCR7 is rv64imafdcv_zba_zbb_zbc_zbs_zkn.
Scheduling model for RVV will be added later.
Overview: https://syntacore.com/products/scr7

---------

Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev at syntacore.com>
Co-authored-by: Elena Lepilkina <elena.lepilkina at syntacore.com>



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