[all-commits] [llvm/llvm-project] dbdf84: [RISCV] Add Syntacore SCR7 processor definition (#...

[Anton Sidorenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbdf84388a825645850a47b035a1f7ab27b789b5
      https://github.com/llvm/llvm-project/commit/dbdf84388a825645850a47b035a1f7ab27b789b5
  Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
  Date:   2024-09-16 (Mon, 16 Sep 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note/riscv.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Syntacore SCR7 processor definition (#108406)

Syntacore SCR7 is a high-performance Linux-capable RISC-V processor
core.
The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march.
Overview: https://syntacore.com/products/scr7

Scheduling model will be added in a subsequent PR.

---------

Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev at syntacore.com>
Co-authored-by: Elena Lepilkina <elena.lepilkina at syntacore.com>



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