[all-commits] [llvm/llvm-project] dfa542: [InitUndef] Enable the InitUndef pass on non-AMDGP...

[Nikita Popov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dfa54298ff6d6e420a1a5b74c070912409713589
      https://github.com/llvm/llvm-project/commit/dfa54298ff6d6e420a1a5b74c070912409713589
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2024-09-16 (Mon, 16 Sep 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
    M llvm/lib/CodeGen/InitUndef.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/R600Subtarget.h
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
    M llvm/lib/Target/ARM/ARMSubtarget.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
    A llvm/test/CodeGen/AArch64/init-undef.mir
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

  Log Message:
  -----------
  [InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)

The InitUndef pass works around a register allocation issue, where undef
operands can be allocated to the same register as early-clobber result
operands. This may lead to ISA constraint violations, where certain
input and output registers are not allowed to overlap.

Originally this pass was implemented for RISCV, and then extended to ARM
in #77770. I've since removed the target-specific parts of the pass in
#106744 and #107885. This PR reduces the pass to use a single
requiresDisjointEarlyClobberAndUndef() target hook and enables it by
default. The hook is disabled for AMDGPU, because overlapping
early-clobber and undef operands are known to be safe for that target,
and we get significant codegen diffs otherwise.

The motivating case is the one in arm64-ldxr-stxr.ll, where we were
previously incorrectly allocating a stxp input and output to the same
register.



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