[all-commits] [llvm/llvm-project] 02e418: [X86] AMD Zen 5 Initial enablement (#107964)

[Ganesh via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02e4186d0b3508e79d78b0ec844518b13a3fe9ea
      https://github.com/llvm/llvm-project/commit/02e4186d0b3508e79d78b0ec844518b13a3fe9ea
  Author: Ganesh <Ganesh.Gopalasubramanian at amd.com>
  Date:   2024-09-13 (Fri, 13 Sep 2024)

  Changed paths:
    M clang/lib/Basic/Targets/X86.cpp
    M clang/test/CodeGen/target-builtin-noerror.c
    M clang/test/Driver/x86-march.c
    M clang/test/Frontend/x86-target-cpu.c
    M clang/test/Misc/target-invalid-cpu-note/x86.c
    M clang/test/Preprocessor/predefined-arch-macros.c
    M compiler-rt/lib/builtins/cpu_model/x86.c
    M llvm/include/llvm/TargetParser/X86TargetParser.def
    M llvm/include/llvm/TargetParser/X86TargetParser.h
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86PfmCounters.td
    M llvm/lib/TargetParser/Host.cpp
    M llvm/lib/TargetParser/X86TargetParser.cpp
    M llvm/test/CodeGen/X86/bypass-slow-division-64.ll
    M llvm/test/CodeGen/X86/cmp16.ll
    M llvm/test/CodeGen/X86/cpus-amd.ll
    M llvm/test/CodeGen/X86/rdpru.ll
    M llvm/test/CodeGen/X86/shuffle-as-shifts.ll
    M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
    M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
    M llvm/test/CodeGen/X86/tuning-shuffle-permilpd-avx512.ll
    M llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll
    M llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll
    M llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll
    M llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
    M llvm/test/CodeGen/X86/vpdpwssd.ll
    M llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
    M llvm/test/MC/X86/x86_long_nop.s
    M llvm/test/Transforms/LoopUnroll/X86/call-remark.ll
    M llvm/test/Transforms/SLPVectorizer/X86/pr63668.ll

  Log Message:
  -----------
  [X86] AMD Zen 5 Initial enablement (#107964)

This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.



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