[all-commits] [llvm/llvm-project] 729439: [lldb][test] Handle failure to get /proc/cpuinfo f...
Mircea Trofin via All-commits
all-commits at lists.llvm.org
Thu Sep 12 11:01:21 PDT 2024
Branch: refs/heads/users/vitalybuka/spr/main.sanitizer-allow-to-override-getdtlsrange
Home: https://github.com/llvm/llvm-project
Commit: 7294396a0878a6bd179fac9aa5c3743832c799f4
https://github.com/llvm/llvm-project/commit/7294396a0878a6bd179fac9aa5c3743832c799f4
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
Log Message:
-----------
[lldb][test] Handle failure to get /proc/cpuinfo from a remote Linux platform (#108183)
I've been testing against qemu-aarch64 using the qemu-user platform,
which doesn't support get-file:
```
AssertionError: False is not true : Command 'platform get-file "/proc/cpuinfo" <...>/TestAArch64LinuxMTEMemoryRegion.test_mte_regions/cpuinfo
Command output:
get-file failed: unimplemented
' did not return successfully
```
QEMU itself does support overriding cpuinfo for the emulated process
(https://gitlab.com/qemu-project/qemu/-/commit/a55b9e72267085957cadb0af0a8811cfbd7c61a9)
however we'd need to be able to read the cpuinfo before the process
starts, so I'm not attempting to use this feature.
Instead if the get-file fails, assume empty cpuinfo so we can at least
carry on testing. I've logged the failure and the reason to the trace so
developers can find it.
```
runCmd: platform get-file "/proc/cpuinfo" <...>/TestAArch64LinuxMTEMemoryRegion.test_mte_regions/cpuinfo
check of return status not required
runCmd failed!
Failed to get /proc/cpuinfo from remote: "get-file failed: unimplemented"
All cpuinfo feature checks will fail.
```
For now this only helps AArch64 but I suspect that RISC-V, being even
more mix and match when it comes to extensions, may need this in future.
And I know we have some folks testing against qemu-riscv at the moment.
Commit: 128bb29e6d9f0aec03ea34e1477efeb561d97f8f
https://github.com/llvm/llvm-project/commit/128bb29e6d9f0aec03ea34e1477efeb561d97f8f
Author: GkvJwa <gkvjwa at gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/utils/gn/build/BUILD.gn
Log Message:
-----------
[gn] Add "/Zc:preprocessor" build flag on windows when using cl.exe (#108252)
Add ```/Zc:preprocessor``` to fix the ```__VA_ARGS__``` expansion error
encountered when building with gn and cl.exe(msvc)
Commit: 958a3371324917c5816b6d0999373a2ae2a1ac2e
https://github.com/llvm/llvm-project/commit/958a3371324917c5816b6d0999373a2ae2a1ac2e
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AArch64/shrink-types.ll
Log Message:
-----------
[VectorCombine] Fix trunc generated between PHINodes (#108228)
Commit: a71407ed3a5f11e9f7ab2060f2557384c643eff4
https://github.com/llvm/llvm-project/commit/a71407ed3a5f11e9f7ab2060f2557384c643eff4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
Log Message:
-----------
[AArch64] Regenerate test checks (NFC)
Commit: 37cf39fdd7ab6dcfbce4633ea5fe743daf2ab358
https://github.com/llvm/llvm-project/commit/37cf39fdd7ab6dcfbce4633ea5fe743daf2ab358
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
Log Message:
-----------
[AArch64] Add test for incorrect stxp register allocation (NFC)
This is a variant of https://github.com/llvm/llvm-project/issues/106380
without inline assembly.
Commit: 63dab72fd5b96cd98bba6d041d08bb2a6f3aaa0a
https://github.com/llvm/llvm-project/commit/63dab72fd5b96cd98bba6d041d08bb2a6f3aaa0a
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[Sema] Remove unused variable 'FromExtType' [NFC]
Last use of the variable was removed in a29afb754fb4
[HLSL] Allow truncation to scalar (#104844)
gcc warned about this:
../../clang/lib/Sema/SemaOverload.cpp:2070:15: warning: unused variable 'FromExtType' [-Wunused-variable]
2070 | if (auto *FromExtType = FromType->getAs<ExtVectorType>()) {
| ^~~~~~~~~~~
Commit: 59731eebf8f24e3e90dc77e91a08d068b529cfc5
https://github.com/llvm/llvm-project/commit/59731eebf8f24e3e90dc77e91a08d068b529cfc5
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
Log Message:
-----------
[bazel] port ded080152acceca5d68014d63f5027a6d8266cbb
Commit: ffcebcdb96c7575d3dc8e6afe70d83d56c241f02
https://github.com/llvm/llvm-project/commit/ffcebcdb96c7575d3dc8e6afe70d83d56c241f02
Author: Lu Weining <luweining at loongson.cn>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
A llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
A llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll
M llvm/unittests/Target/LoongArch/InstSizes.cpp
Log Message:
-----------
[LoongArch] Implement Statepoint lowering (#108212)
The functionality has been validated in OpenHarmony's arkcompiler.
Commit: adde85e7c3ade54b22c99d405fc9c3add869db0a
https://github.com/llvm/llvm-project/commit/adde85e7c3ade54b22c99d405fc9c3add869db0a
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A lldb/test/API/functionalities/watchpoint/categories
Log Message:
-----------
[lldb][test] Mark some more watchpoint tests
Noticed when testing with qemu-aarch64 that does not support watchpoints.
Commit: ecf260e1dd8fb1c3d81e6f8af99907ae250058cb
https://github.com/llvm/llvm-project/commit/ecf260e1dd8fb1c3d81e6f8af99907ae250058cb
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
R llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
R llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
R llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
Log Message:
-----------
[RISCV] Merge bf16 tests into respective tests. NFC
I added these in #108245, but given the sheer number of tests that
will need to be added to cover bf16 promotion to f32 it seems better
to keep them in one place to avoid an explosion of files.
Commit: 89c10e27d8b4d5f44998aad9abd2590d9f96c5df
https://github.com/llvm/llvm-project/commit/89c10e27d8b4d5f44998aad9abd2590d9f96c5df
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/fp-min-max-abs.ll
M llvm/test/Analysis/CostModel/RISCV/fround.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll
M llvm/test/Analysis/CostModel/RISCV/splice.ll
Log Message:
-----------
[RISCV] Add zvfhmin cost model test coverage. NFC
This adds tests coverage for zvfhmin and halfs in general in the cost
model tests.
Some existing half tests were split into separate functions so that if
the check prefixes diverge it won't affect the rest of the non-half
instructions.
Whilst we're here, also remove the redundant
-riscv-vector-bits-min=128 and declares.
Commit: 849d1b8b1f1fc16dc28b07da358515a52b79ea81
https://github.com/llvm/llvm-project/commit/849d1b8b1f1fc16dc28b07da358515a52b79ea81
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaTemplate/pack-deduction.cpp
Log Message:
-----------
[clang] Do not substitute parameter pack while retaining the pack expansion (#108197)
(In reference to https://github.com/llvm/llvm-project/pull/108197/commits/5901d82ea0543074853b963f7dc9106a6fe3bcee)
Consider when `Input[I]` is a `VarDecl` with parameter pack. We would
have already expanded the pack before the code change in the loop`for
(unsigned I = 0; I != *NumExpansions; ++I) {`.
Now in `if (RetainExpansion) {`, without this change, we continue to
substitute the pack in the pattern even when we do not have meaningful
`ArgumentPackSubstitutionIndex` set.
This leads to use of an invalid pack substitution index in
`TemplateInstantiator::TransformFunctionParmPackRefExpr` in
`TransformedDecl = (*Pack)[getSema().ArgumentPackSubstitutionIndex];`
This change sets `ArgumentPackSubstitutionIndex` to `-1` while retaining
expansion to instruct `TransformFunctionParmPackRefExpr` to build
`FunctionParmPackExpr` instead of substituting the param pack.
---
There are other instances of `RetainExpansion` and IIUC, they should
also unset the `ArgumentPackSubstitutionIndex`. It would be great if
someone can verify my understanding. If this is correct then we could
instead have a `ArgumentPackSubstitutionIndexRAII` as part of
`ForgetPartiallySubstitutedPackRAII`.
EDIT: I have moved this to `ForgetPartiallySubstitutedPackRAII`.
Fixes https://github.com/llvm/llvm-project/issues/63819
Fixes https://github.com/llvm/llvm-project/issues/107560
Commit: f22a8d18229fe94fe340afbf02ad9592ca199784
https://github.com/llvm/llvm-project/commit/f22a8d18229fe94fe340afbf02ad9592ca199784
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Fix modify_global diagnostics in C++11 (#108358)
We shouldn't emit this until C++14.
Commit: ddd2af3c5a076f2c5f2024019067b206d1b411b4
https://github.com/llvm/llvm-project/commit/ddd2af3c5a076f2c5f2024019067b206d1b411b4
Author: Hans <hans at hanshq.net>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/tools/CMakeLists.txt
R clang/tools/clang-format-vs/.gitignore
R clang/tools/clang-format-vs/CMakeLists.txt
R clang/tools/clang-format-vs/ClangFormat.sln
R clang/tools/clang-format-vs/ClangFormat/ClangFormat.csproj
R clang/tools/clang-format-vs/ClangFormat/ClangFormat.vsct
R clang/tools/clang-format-vs/ClangFormat/ClangFormatPackage.cs
R clang/tools/clang-format-vs/ClangFormat/GlobalSuppressions.cs
R clang/tools/clang-format-vs/ClangFormat/Guids.cs
R clang/tools/clang-format-vs/ClangFormat/PkgCmdID.cs
R clang/tools/clang-format-vs/ClangFormat/Properties/AssemblyInfo.cs
R clang/tools/clang-format-vs/ClangFormat/Resources.Designer.cs
R clang/tools/clang-format-vs/ClangFormat/Resources.resx
R clang/tools/clang-format-vs/ClangFormat/Resources/Images_32bit.bmp
R clang/tools/clang-format-vs/ClangFormat/Resources/Package.ico
R clang/tools/clang-format-vs/ClangFormat/RunningDocTableEventsDispatcher.cs
R clang/tools/clang-format-vs/ClangFormat/VSPackage.resx
R clang/tools/clang-format-vs/ClangFormat/Vsix.cs
R clang/tools/clang-format-vs/ClangFormat/license.txt
R clang/tools/clang-format-vs/ClangFormat/packages.config
R clang/tools/clang-format-vs/README.txt
R clang/tools/clang-format-vs/source.extension.vsixmanifest.in
M llvm/utils/release/build_llvm_release.bat
Log Message:
-----------
Delete the clang-format Visual Studio plugin code (#108342)
This was obsoleted by Visual Studio providing built-in support for
running clang-format in VS2017.
We haven't shipped it for years (since
10d2195305ac49605f2b7b6a25a4076c31923191), never got it working with
VS2019, and never even tried with VS2022.
It's time to retire the code.
Commit: d5d6b447840f80a78047cf5ba769e4a09b44b83e
https://github.com/llvm/llvm-project/commit/d5d6b447840f80a78047cf5ba769e4a09b44b83e
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/lib/Support/FormatVariadic.cpp
M llvm/unittests/Support/FormatVariadicTest.cpp
Log Message:
-----------
[Support] Add automatic index assignment in formatv (#107459)
Make index in replacement field optional. It will be automatically
assigned in incremental order by formatv.
Make mixed use of automatic and explicit indices an error that will fail
validation.
Adopt uses of formatv() within FormatVariadic to use automatic index.
Commit: ebb979d6363be97ece020bb52477430025996962
https://github.com/llvm/llvm-project/commit/ebb979d6363be97ece020bb52477430025996962
Author: Nico Weber <thakis at chromium.org>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port 118f120eaab8d
Commit: 36ad0720de623221e3cc17d30f4173331c099a72
https://github.com/llvm/llvm-project/commit/36ad0720de623221e3cc17d30f4173331c099a72
Author: Aditi Medhane <Aditi.Medhane at amd.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
Log Message:
-----------
[AMDGPU] Autogenerate checks for phi-vgpr-input-moveimm.mir (#108372)
Update the MIR checks for phi-vgpr-input-moveimm testcase.
Commit: 36adf8ecedb64047021265a1e1730773d3b3a9e8
https://github.com/llvm/llvm-project/commit/36adf8ecedb64047021265a1e1730773d3b3a9e8
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
Log Message:
-----------
[NFC][Analysis] Add more SCEV tests for ptr inductions (#108210)
I've added more tests to
Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
to cover more cases of ptr inductions, in particular highlighting what
seems to be a disparity between single exit and multiple exit loops.
Commit: c657a6f6aa7e802d65aba84b8b3fe2eb5e2459d8
https://github.com/llvm/llvm-project/commit/c657a6f6aa7e802d65aba84b8b3fe2eb5e2459d8
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
Log Message:
-----------
[AMDGPU] Fix selection of s_load_b96 on GFX11 (#108029)
Fix a bug which resulted in selection of s_load_b96 on GFX11, which only
exists in GFX12.
The root cause was a mismatch between legalization and selection. The
condition used to check that the load was uniform in legalization
(SITargetLowering::LowerLOAD) was "!Op->isDivergent()". The condition
used to detect a non-uniform load during selection
(AMDGPUDAGToDAGISel::isUniformLoad()) was
"N->isDivergent() && !AMDGPUInstrInfo::isUniformMMO(MMO)". This makes a
difference when IR uniformity analysis has more information than SDAG's
built in analysis. In the test case this is because IR UA reports that
everything is uniform if isSingleLaneExecution() returns true, e.g. if
the specified max flat workgroup size is 1, but SDAG does not have this
optimization.
The immediate fix is to use the same condition to detect uniform loads
in legalization and selection. In future SDAG should learn about
isSingleLaneExecution(), and then it could probably stop relying on IR
metadata to detect uniform loads.
Commit: bf8101e4fd1a532aed4c6b6a33d202e143ce303f
https://github.com/llvm/llvm-project/commit/bf8101e4fd1a532aed4c6b6a33d202e143ce303f
Author: Joe Faulls <67795994+joe-img at users.noreply.github.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
Log Message:
-----------
[CodeGen] Clear InitUndef pass new register cache between pass runs (#90967)
Multiple invocations of the pass could interfere with eachother,
preventing some undefs being initialised.
I found it very difficult to create a unit test for this due to it being
dependent on particular allocations of a previous function. However, the
bug can be observed here: https://godbolt.org/z/7xnMo41Gv with the
creation of the illegal instruction `vnsrl.wi v9, v8, 0`
Commit: 229f391f836c9250b7e0c3824e7152748bab220e
https://github.com/llvm/llvm-project/commit/229f391f836c9250b7e0c3824e7152748bab220e
Author: rjmansfield <rjmansfield at users.noreply.github.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/tools/dsymutil/Options.td
Log Message:
-----------
[dsymutil] Fix whitespace issues and typo in HelpText. (#108310)
Co-authored-by: Ryan Mansfield <ryan_mansfield at apple.com>
Commit: 6093c26ac9e1f6ba919c0c3e18c6425ba1a625f8
https://github.com/llvm/llvm-project/commit/6093c26ac9e1f6ba919c0c3e18c6425ba1a625f8
Author: Matthias Springer <me at m-sp.org>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Align handling of dropped values (#106760)
Handle dropped block arguments and dropped op results in the same way:
build a source materialization (that may fold away if unused). This
simplifies the code base a bit and makes it possible to merge
`legalizeConvertedArgumentTypes` and `legalizeConvertedOpResultTypes` in
a future commit. These two functions are almost doing the same thing
now.
As a side effect, this commit also changes the dialect conversion such
that temporary circular cast ops are no longer generated. (There was a
workaround in #107109 that can now be removed again.) Example:
```
%0 = "builtin.unrealized_conversion_cast"(%1) : (!a) -> !b
%1 = "builtin.unrealized_conversion_cast"(%0) : (!b) -> !a
// No further uses of %0, %1.
```
This happened when:
1. An op was erased. (No replacement values provided.)
2. A conversion pattern for another op builds a replacement value for
the erased op's results (first cast op) during `remapValues`, but that
SSA value is not used during the pattern application.
3. During the finalization phase, `legalizeConvertedOpResultTypes`
thinks that the erased op is alive because of the cast op that was built
in Step 2. It builds a cast from that replacement value to the original
type.
4. During the commit phase, all uses of the original op are replaced
with the casted value produced in Step 3. We have generated circular IR.
This problem can be avoided by making sure that source materializations
are generated for all dropped results. This ensures that we always have
some replacement SSA value in the mapping. Previously, we sometimes had
a value mapped and sometimes not. (No more special casing is needed
anymore to distinguish between "value dropped" or "value replaced with
SSA value".)
Commit: b9674cb10fbe34d54bdfaa584e2eb89b65034e91
https://github.com/llvm/llvm-project/commit/b9674cb10fbe34d54bdfaa584e2eb89b65034e91
Author: Matthias Springer <me at m-sp.org>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
Log Message:
-----------
[mlir][SPIRV] Make test case more robust (#108388)
This commit is in preparation of #108381, which changes the insertion
point source materializations during a block type conversion slightly.
Commit: 7c82b56116d402aa6b86d734ea481a1e90a2f1c3
https://github.com/llvm/llvm-project/commit/7c82b56116d402aa6b86d734ea481a1e90a2f1c3
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M lld/COFF/Chunks.h
Log Message:
-----------
[LLD][COFF] Define importThunkARM64EC as uint8_t array to fix big-endian hosts.
Fixes #107931, spotted by Nikita Popov.
Commit: 5237f0dbcbb3883d81cb872d386547c7ff416894
https://github.com/llvm/llvm-project/commit/5237f0dbcbb3883d81cb872d386547c7ff416894
Author: Aditi Medhane <Aditi.Medhane at amd.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
Log Message:
-----------
[AMDGPU] Precommit and Modify `phi_moveimm_subreg_input` testcase (#108389)
- Updated `phi_moveimm_subreg_input` test case to introduce
sub-registers as PHI input operands.
Currently subreg is making the testcase in non-SSA format, need to fix
this by giving subreg as an input operand to PHI instead defining the
subreg register.
This change is relevant for : [[AMDGPU] Add MachineVerifier check to
detect illegal copies from vector register to SGPR
](https://github.com/llvm/llvm-project/pull/105494)
Commit: b43302372f592fd48a22d32b2603f8efee40a88e
https://github.com/llvm/llvm-project/commit/b43302372f592fd48a22d32b2603f8efee40a88e
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/tools/libclang/CXStoredDiagnostic.cpp
Log Message:
-----------
[Clang][NFC] Remove trailing whitespace from clang/tools/libclang/CXStoredDIagnostic.cpp
Commit: 1642f64b525e1d73ca5a0456a187433c7f0eff4c
https://github.com/llvm/llvm-project/commit/1642f64b525e1d73ca5a0456a187433c7f0eff4c
Author: David Green <david.green at arm.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
Log Message:
-----------
[AArch64] Replace _Ncyc_ with _Nc_ in Neoverse scheduling models.
This brings them in line with the other Neoverse scheduling models, reducing
the amount of differences between them.
Commit: 99174842aedf9aa571bdb23d07566965ff3c21e3
https://github.com/llvm/llvm-project/commit/99174842aedf9aa571bdb23d07566965ff3c21e3
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/UserDocumentation.rst
M libcxx/include/__config
M libcxx/include/__stop_token/atomic_unique_lock.h
M libcxx/include/__stop_token/stop_callback.h
M libcxx/include/__stop_token/stop_source.h
M libcxx/include/__stop_token/stop_token.h
M libcxx/include/__thread/jthread.h
M libcxx/include/condition_variable
M libcxx/include/version
M libcxx/modules/std/stop_token.inc
M libcxx/modules/std/thread.inc
M libcxx/test/libcxx/experimental/fexperimental-library.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/stop_token.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/thread.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp
M libcxx/test/support/make_test_thread.h
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Make std::jthread supported in non-experimental mode (#107900)
We waited before supporting std::jthread fully because we wanted to
investigate other implementation strategies (in particular one involving
std::mutex). Since then, we did some benchmarking and decided that we
wouldn't be moving forward with std::mutex. Hence, there is no real
reason to punt on making std::jthread & friends non-experimental.
Commit: dbc90b55e832695c96d8dc1427e9df3bfeb73e5a
https://github.com/llvm/llvm-project/commit/dbc90b55e832695c96d8dc1427e9df3bfeb73e5a
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[clang][TableGen] Change AttrEmitter to use const RecordKeeper (#108269)
Change AttrEmitter to use const RecordKeeper.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
Commit: b6ff8ed5d4d03b28e41b73ef8e76ce94a8fa76f0
https://github.com/llvm/llvm-project/commit/b6ff8ed5d4d03b28e41b73ef8e76ce94a8fa76f0
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[clang][TableGen] Change AST Nodes Emitter to use const RecordKeeper (#108270)
Change AST Nodes Emitter to use const RecordKeeper.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
Commit: 7e74472801486cc702fba3e831c8fcd77c120142
https://github.com/llvm/llvm-project/commit/7e74472801486cc702fba3e831c8fcd77c120142
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbutil.py
Log Message:
-----------
[lldb][testing] Check all stop reasons in get_threads_stopped_at_breakpoint_id (#108281)
If multiple breakpoints are hit at the same time, multiple stop reasons
are reported, one per breakpoint.
Currently, `get_threads_stopped_at_breakpoint_id` only checks the first
such reason.
Commit: c0b3e491cc9afe10c310334ceac1971482bb0410
https://github.com/llvm/llvm-project/commit/c0b3e491cc9afe10c310334ceac1971482bb0410
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Target/Mips/MipsFastISel.cpp
A llvm/test/CodeGen/Mips/Fast-ISel/underaligned-load-store.ll
Log Message:
-----------
[llvm][Mips] Bail on underaligned loads/stores in FastISel. (#106231)
We encountered this problem in Zig, causing all of our
`mips(el)-linux-gnueabi*` tests to fail:
https://github.com/ziglang/zig/issues/21215
For these unusual cases, let's just bail in `MipsFastISel` since
`MipsTargetLowering` can handle them fine.
Note: I don't have commit access.
Commit: 64dba97a981393c21cff8bddc0d2272535da45d5
https://github.com/llvm/llvm-project/commit/64dba97a981393c21cff8bddc0d2272535da45d5
Author: Michael Park <mcypark at gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/lib/Parse/ParseStmt.cpp
Log Message:
-----------
[NFC] Fix an inaccurate comment about typo-correction. (#108143)
The comment describes "If the identifier was typo-corrected", but it
doesn't need to have been typo-corrected, just being annotated is enough
to retry.
Commit: ef7a847be2db0325fe8bbad7febac9e42c96d232
https://github.com/llvm/llvm-project/commit/ef7a847be2db0325fe8bbad7febac9e42c96d232
Author: Amr Hesham <amr96 at programmer.net>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
Log Message:
-----------
[LoopUnswitch] Remove redundant condition. (NFC) (#107893)
Remove redundant condition from '!A || (A && B)' to '!A || B'
Fixes: #99799
Commit: a409ebc1fc136be4004073a12cd7f847a5f3a588
https://github.com/llvm/llvm-project/commit/a409ebc1fc136be4004073a12cd7f847a5f3a588
Author: Malay Sanghi <malay.sanghi at intel.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.def
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512satcvtdsintrin.h
A clang/lib/Headers/avx10_2satcvtdsintrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-errors.c
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64-error.c
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c
A clang/test/CodeGen/X86/avx10_2satcvtds-builtins-errors.c
A clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c
A clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
A llvm/test/CodeGen/X86/avx10_2_512satcvtds-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll
A llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll
A llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-64.txt
A llvm/test/MC/X86/avx10_2satcvtds-32-att.s
A llvm/test/MC/X86/avx10_2satcvtds-32-intel.s
A llvm/test/MC/X86/avx10_2satcvtds-64-att.s
A llvm/test/MC/X86/avx10_2satcvtds-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][AVX10.2] Support AVX10.2-SATCVT-DS new instructions. (#102592)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
Commit: 90a0be9482ad00acc1772440f13656190ec1ac22
https://github.com/llvm/llvm-project/commit/90a0be9482ad00acc1772440f13656190ec1ac22
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[mlir][LLVM] Refactor how range() annotations are handled for ROCDL intrinsics (#107658)
This commit introduces a ConstantRange attribute to match the
ConstantRange attribute type present in LLVM IR.
It then refactors the LLVM_IntrOpBase so that the basic part of the
intrinsic builder code can be re-used without needing to copy it or
get rid of important context. This, along with adding code for
handling an optional `range` attribute to that same base, allows us to
make the support for range() annotations generic without adding
another bit to IntrOpBase.
This commit then updates the lowering of index intrinsic operations to
use the new ConstantRange attribute and fixes a bug (where we'd be
subtracting 1 from upper bounds instead of adding it on operations
like gpu.block_dim) along the way.
The point of these changes is to enable these range annotations to be
used for the corresponding NVVM operations in a future commit.
Commit: 9596e83b2aa9017f4ebec3c150ca3aadd047762b
https://github.com/llvm/llvm-project/commit/9596e83b2aa9017f4ebec3c150ca3aadd047762b
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
M mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir
Log Message:
-----------
[mlir][AMDGPU] Enable emulating vector buffer_atomic_fadd on gfx11 (#108312)
* Fix a bug introduced by the Chipset refactoring in #107720 where
atomics emulation for adds was mistakenly applied to gfx11+
* Add the case needed for gfx11+ atomic emulation, namely that gfx11
doesn't support atomically adding a v2f16 or v2bf16, thus requiring
MLIR-level legalization for buffer intrinsics that attempt to do such an
addition
* Add tests, including tests for gfx11 atomic emulation
Co-authored-by: Manupa Karunaratne <manupa.karunaratne at amd.com>
Commit: 8cf3eb49a5d9831620b290b9a0686149bd438267
https://github.com/llvm/llvm-project/commit/8cf3eb49a5d9831620b290b9a0686149bd438267
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port a409ebc1fc13
Commit: 2e30f8d114e1406b35dc63868a92f4279330251b
https://github.com/llvm/llvm-project/commit/2e30f8d114e1406b35dc63868a92f4279330251b
Author: Balazs Benics <benicsbalazs at gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/test/Analysis/fread.c
Log Message:
-----------
[analyzer] Fix StreamChecker crash in fread modeling (#108393)
In #93408
https://github.com/llvm/llvm-project/commit/69bc159142c6e4ed168e32a6168392d396f891de
I refined how invalidation is done for `fread`. It can crash, if the
"size" or "count" parameters of "fread" is a perfectly constrained
negative value. In such cases, when it will try to allocate a
SmallVector with a negative size, which will cause a crash.
To mitigate this issue, let's just guard against negative values.
CPP-3247
Commit: 43fd2c401edd4f3ca0c687dd6937c2603fb15f71
https://github.com/llvm/llvm-project/commit/43fd2c401edd4f3ca0c687dd6937c2603fb15f71
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
A clang/test/AST/ByteCode/const-base-cast.cpp
M clang/test/CodeGenCXX/const-base-cast.cpp
Log Message:
-----------
[clang][bytecode] Implement base casts on integral pointers (#108340)
Get the right offset to apply from the RecordLayout.
Commit: bd8d432d7bd0891132ae69daa70e18ba387df43f
https://github.com/llvm/llvm-project/commit/bd8d432d7bd0891132ae69daa70e18ba387df43f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
M clang/test/CodeGenObjC/boxing.m
Log Message:
-----------
[clang][bytecode] Add support for creating dummies for expressions (#108394)
And use that to fix VisitObjCBoxedExprs.
Commit: 8c0551503219b8e1da7dd6c24de1d9e79cb7cae6
https://github.com/llvm/llvm-project/commit/8c0551503219b8e1da7dd6c24de1d9e79cb7cae6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/RISCV/half-convert.ll
Log Message:
-----------
[LegalizeIntegerTypes] Simplify ExpandIntRes_FP_TO_XINT when operand needs to be SoftPromoted. (#107634)
Create an FP_EXTEND instead of handling the soft promote directly. This
FP_EXTEND will be visited and soft promoted itself.
This removes a zero extend from the generated code when the f32 type is
itself softened. Previously we softened it as an fp16_to_fp which sees
the operand as an integer type so we extend it. When we soften the
result as an fp_extend we see the source as f16 and don't extend. It
only becomes an integer inside call lowering not by type legalization.
If this extend is really necessary, then we have an issue when an
f16->f32 fp_extend exists in the source and f32 needs to be softened.
This simplifies part of #102503.
Commit: 859b785bb6a1ee20ffca58102d877fc9a4a639e4
https://github.com/llvm/llvm-project/commit/859b785bb6a1ee20ffca58102d877fc9a4a639e4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
Log Message:
-----------
[RISCV] Restructure CC_RISCV_FastCC to reduce code duplication. NFC (#107671)
Move GPR handling closer to the end so we can share it with the indirect
handling for vector. Use a single block for storing any type to the
stack.
Commit: e42f4734c61ac139eba6f880e204c5231b431b9b
https://github.com/llvm/llvm-project/commit/e42f4734c61ac139eba6f880e204c5231b431b9b
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
Log Message:
-----------
Reland "[NVPTX] Support copysign PTX instruction" (#108125)
Lower `fcopysign` SDNodes into `copysign` PTX instructions where
possible. See [PTX ISA: 9.7.3.2. Floating Point Instructions: copysign]
(https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-copysign).
Copysign SDNodes with mismatched types are expanded as before, since the
PTX instruction requires the types to match.
Commit: 73535076f2c517fd04c43cccab4c47bd38b39d49
https://github.com/llvm/llvm-project/commit/73535076f2c517fd04c43cccab4c47bd38b39d49
Author: Saleem Abdulrasool <abdulras at thebrowser.company>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64.h
Log Message:
-----------
builtins: replicate `aarch64.c` change into `aarch64.h`
Perform the same macro expansion in the header to improve handling
the various ARM64 environments which use different CPU architecture
identification macro spellings.
Commit: 1ad84d7961ec3ddab9233370066110ecaa5eb329
https://github.com/llvm/llvm-project/commit/1ad84d7961ec3ddab9233370066110ecaa5eb329
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
A llvm/test/CodeGen/Mips/ins.ll
Log Message:
-----------
[Mips] Optimize `or (and $src1, mask), (shl $src2, shift)` to `ins` (#103017)
Optimize `$dst = or (and $src1, (2**size0 - 1)), (shl $src2, size0)` to
`ins $src1, $src2, pos, size`,
where `pos = size0, size = 32 - pos`.
Fix #90325
Commit: fc1c481cf45b41137a08a753c543d8a69d393671
https://github.com/llvm/llvm-project/commit/fc1c481cf45b41137a08a753c543d8a69d393671
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
M flang/module/__fortran_builtins.f90
M flang/module/__fortran_ieee_exceptions.f90
M flang/module/ieee_arithmetic.f90
M flang/module/iso_fortran_env.f90
M flang/test/Driver/include-header.f90
A flang/test/Preprocessing/include-file.h
A flang/test/Preprocessing/include-line.F90
Log Message:
-----------
[flang][preprocessor] Change handling of macros in text from Fortran … (#108113)
…INCLUDE lines
The compiler current treats an INCLUDE line as essentially a synonym for
a preprocessing #include directive. The causes macros that have been
defined at the point where the INCLUDE line is processed to be replaced
within the text of the included file.
This behavior is surprising to users who expect an INCLUDE line to be
expanded into its contents *after* preprocessing has been applied to the
original source file, with no further macro expansion.
Change INCLUDE line processing to use a fresh instance of Preprocessor
containing no macro definitions except _CUDA in CUDA Fortran
compilations and, if the original file was being preprocessed, the
standard definitions of __FILE__, __LINE__, and so forth.
Commit: c6ca13db41e135d593e33f85cf955d2c041580c3
https://github.com/llvm/llvm-project/commit/c6ca13db41e135d593e33f85cf955d2c041580c3
Author: Luke Lau <luke at igalia.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Log Message:
-----------
[RISCV] Lower interleave + deinterleave for zvfhmin and zvfbfmin (#108404)
Fortunately f16 and bf16 are always < EEW, so we can always lower via
widening or narrowing. This means we don't need to add patterns for
vrgather_vv_vl just yet.
Commit: 8ed8210690816084159a166bf698c16ce9ed6a9b
https://github.com/llvm/llvm-project/commit/8ed8210690816084159a166bf698c16ce9ed6a9b
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/local-vs-global.f90
Log Message:
-----------
[flang] Downgrade error message to warning (#108115)
It is a non-mandatory error to reference an external procedure via an
implicit interface declaration (EXTERNAL or PROCEDURE()) when the
external procedure has an interface that requires the presence of an
explicit interface to be called.
Until now, the compiler has issued a fatal error message from semantics
for this situation. But (1) there are situations, such as passing such
an EXTERNAL as an actual argument, or as the target of a procedure
pointer assignment, where little or no harm is done, (2) other compilers
don't/can't detect this error, even when the procedure's definition is
in the same source file, and (3) it shows up in some real applications.
So downgrade this error to a stern warning. Perhaps in the future the
compiler could resume emission of a hard error in the cases where the
EXTERNAL procedure is actually known to be called via its implicit
interface.
Commit: eb8cc89295fca2d6436afc38938ca5365a82707c
https://github.com/llvm/llvm-project/commit/eb8cc89295fca2d6436afc38938ca5365a82707c
Author: cchen <chichun.chen at hpe.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[NFC] Claim OpenMP feature - target_device selector set
Commit: 1d3bcf99bd0698fb5ebf5fccc24cebf2596dce0a
https://github.com/llvm/llvm-project/commit/1d3bcf99bd0698fb5ebf5fccc24cebf2596dce0a
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M flang/lib/Evaluate/intrinsics.cpp
A flang/test/Semantics/kinds06.f90
Log Message:
-----------
[flang] Better error recovery for REAL(x, [KIND=]bad) (#108222)
There's two entries in the intrinsic table for REAL; the first handles
the REAL(z) case of a COMPLEX argument, and the second handles the data
type/kind conversion case.
In the case of REAL(x,bad) with a bad or unsupported kind of REAL,
neither table entry was matching. In the event of an unrecognized
intrinsic function, the compiler emits the first error message that
resulted, which was confusing here because it was a complaint about
having too many arguments.
Reversing the order of the intrinsic table entries would fix the error
message, but would also have broken REAL(z) with a complex argument,
since it would then be treated as REAL(z,KIND=KIND(0.)) rather than
REAL(z,KIND=KIND(z)).
The fix is to let the second entry "hit" with improved error recovery.
Commit: 1595ca435ca9e85a3f693267b5f928bf3cfc2cc1
https://github.com/llvm/llvm-project/commit/1595ca435ca9e85a3f693267b5f928bf3cfc2cc1
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M flang/lib/Semantics/check-call.cpp
A flang/test/Semantics/elemental02.f90
Log Message:
-----------
[flang] Catch whole assumed-size array passed to elemental (#108239)
A whole assumed-size array is not a valid argument to an elemental
procedure (intrinsic or otherwise).
Commit: 524201881562d696841561e44f0a70a7cc7dc18d
https://github.com/llvm/llvm-project/commit/524201881562d696841561e44f0a70a7cc7dc18d
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M flang/include/flang/Semantics/expression.h
M flang/lib/Semantics/expression.cpp
M flang/test/Semantics/expr-errors06.f90
Log Message:
-----------
[flang] Catch attempts to subscribe empty arrays (#108246)
An array that has one or more empty dimensions cannot have subscripts
unless there's a possibility that they constitute an empty array
section.
We previously only checked that constant subscripts are in bounds.
Commit: 7aad87312a00a6ce4cdf7fd5bd5d597ff413a600
https://github.com/llvm/llvm-project/commit/7aad87312a00a6ce4cdf7fd5bd5d597ff413a600
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M flang/runtime/edit-input.cpp
M flang/unittests/Runtime/Namelist.cpp
Log Message:
-----------
[flang][runtime] Accept some real input for integer NAMELIST (#108268)
A few other Fortran compilers silently accept real values for integer
variables in NAMELIST input. Handling an exponent would be difficult,
but it's easy to skip and ignore a fractional part when one is present.
Commit: a16164d0c258b284117f8c150efaef891e9aa057
https://github.com/llvm/llvm-project/commit/a16164d0c258b284117f8c150efaef891e9aa057
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[MLIR][ROCDL] Add dynamically legal ops to LowerGpuOpsToROCDLOpsPass (#108302)
Similar to https://github.com/llvm/llvm-project/pull/108266
After https://github.com/llvm/llvm-project/pull/102971
It is legal to generate `LLVM::ExpOp` and `LLVM::LogOp` if the type is
is a float16 or float32
Commit: a6a547f18d99f0b0bf5ffac55443d687200f972d
https://github.com/llvm/llvm-project/commit/a6a547f18d99f0b0bf5ffac55443d687200f972d
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/test/Shell/SymbolFile/DWARF/no_unique_address-with-bitfields.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang] Prevent unnamed bitfield creation in the presence of overlapping fields (#108343)
This bug surfaced after https://github.com/llvm/llvm-project/pull/105865
(currently reverted, but blocked on this to be relanded).
Because Clang doesn't emit `DW_TAG_member`s for unnamed bitfields, LLDB
has to make an educated guess about whether they existed in the source.
It does so by checking whether there is a gap between where the last
field ended and the currently parsed field starts. In the example test
case, the empty field `padding` was folded into the storage of `data`.
Because the `bit_offset` of `padding` is `0x0` and its `DW_AT_byte_size`
is `0x1`, LLDB thinks the field ends at `0x1` (not quite because we
first round the size to a word size, but this is an implementation
detail), erroneously deducing that there's a gap between `flag` and
`padding`.
This patch adds the notion of "effective field end", which accounts for
fields that share storage. It is set to the end of the storage that the
two fields occupy. Then we use this to check for gaps in the unnamed
bitfield creation logic.
Commit: ee40ffd1ee3a13f504cfca6bae5e65c868a5b762
https://github.com/llvm/llvm-project/commit/ee40ffd1ee3a13f504cfca6bae5e65c868a5b762
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/test/tools/llvm-mca/X86/Znver4/zero-idioms.s
Log Message:
-----------
[X86] Recognize VPXORDZrr as a zero-idiom on Znver4 (#108314)
This patch adds information about VPXORDZrr to the znver4 scheduling
model, particularly that it is a zero-idiom.
This fixes a proximal cause of #108157.
Commit: ab96409180aaad5417030f06a386253722a99d71
https://github.com/llvm/llvm-project/commit/ab96409180aaad5417030f06a386253722a99d71
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M .github/workflows/release-binaries.yml
Log Message:
-----------
workflows/release-binaries: Fix automatic upload (#107315)
Commit: 6eb3519fd70bb50bc3773fdf0bf9435dae2abfe7
https://github.com/llvm/llvm-project/commit/6eb3519fd70bb50bc3773fdf0bf9435dae2abfe7
Author: Chris B <chris.bieneman at me.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/lib/Sema/SemaInit.cpp
M clang/test/AST/HLSL/vector-constructors.hlsl
Log Message:
-----------
[HLSL] Allow narrowing in initialization lists (#108035)
HLSL's initialization lists are _extremely_ generous about allowing
conversions. This change demotes the C++11 warning to the legacy warning
when in HLSL mode.
Required for #56067
Commit: bea2f2511b69521dc73766b8e3503f11e378113b
https://github.com/llvm/llvm-project/commit/bea2f2511b69521dc73766b8e3503f11e378113b
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/utils/gn/build/toolchain/target_flags.gni
M llvm/utils/gn/secondary/compiler-rt/lib/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/asan/BUILD.gn
Log Message:
-----------
[gn build] Port win asan runtime rules (#108293)
Windows doesn't have a static runtime after #107899.
Commit: 9e2bb418b4a21fb8ca1fe83fb01a26e3f72d59a1
https://github.com/llvm/llvm-project/commit/9e2bb418b4a21fb8ca1fe83fb01a26e3f72d59a1
Author: Marc Auberer <marc.auberer at chillibits.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT][NFC] Remove unused parameter from DenseMap::InsertIntoBucketImpl (#108382)
Remove unused parameter `Key` from `InsertIntoBucketImpl`
Commit: 2d47a0baba6f18b5cdf14c007e01b79e37d15c72
https://github.com/llvm/llvm-project/commit/2d47a0baba6f18b5cdf14c007e01b79e37d15c72
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/step.hlsl
A clang/test/SemaHLSL/BuiltIns/step-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/step.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll
Log Message:
-----------
Add step builtins and step HLSL function to DirectX and SPIR-V backend (#106471)
This PR adds the step intrinsic and an HLSL function that uses it.
The SPIRV backend is also implemented.
Used https://github.com/llvm/llvm-project/pull/102683 as a reference.
Fixes https://github.com/llvm/llvm-project/issues/99157
Commit: ee9264522caacad34c5dc2bfb239c223229b870d
https://github.com/llvm/llvm-project/commit/ee9264522caacad34c5dc2bfb239c223229b870d
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_tls_get_addr.cpp
Log Message:
-----------
[sanitizer] Change GetDTLSRange (#108345)
We only need to change size, tls_beg should be unchanged.
Commit: a30b1d5a38fb7c371293c2b90d0200d0353a3be1
https://github.com/llvm/llvm-project/commit/a30b1d5a38fb7c371293c2b90d0200d0353a3be1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
Log Message:
-----------
[SelectionDAG] Use Register in a few places in InstrEmitter. NFC
Commit: 81935c5e96ef9310bb16a18ea1d74fb64eaf43da
https://github.com/llvm/llvm-project/commit/81935c5e96ef9310bb16a18ea1d74fb64eaf43da
Author: Charlie Barto <chbarto at microsoft.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[compiler-rt] [MSVC] Detect MSVC as a compiler-id for lit. (#108255)
This is only for "real" msvc and is to support running sanitizer tests
with "real" MSVC. Most compiler-rt tests do not yet pass with msvc,
which will be addressed in future PRs for asan, sanitizer_common, and
the fuzzer.
We've been using these changes to lit to run CI for the version of
address sanitizer that ships with MSVC, by upstreaming them we can avoid
being broken by future lit changes and allow contributors (importantly
_us_) to run the MSVC tests on changes developed in the open.
Commit: 885ac29910a23db923292fe3fc09d0ec105186dc
https://github.com/llvm/llvm-project/commit/885ac29910a23db923292fe3fc09d0ec105186dc
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/lib/ProfileData/PGOCtxProfReader.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
Log Message:
-----------
[nfc][ctx_prof] Change some internal "set" types
- the set used for targets under a callsite is simpler to use if iterators
are stable (it gets manipulated during updates)
- the set used to fetch the transitive closure of GUIDs under a node can
be left as a choice to the user.
Commit: 8d747e19fd12c335b8b7428142ae18bbecc8270f
https://github.com/llvm/llvm-project/commit/8d747e19fd12c335b8b7428142ae18bbecc8270f
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M .github/workflows/release-binaries.yml
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsX86.def
M clang/include/clang/Basic/BuiltinsX86_64.def
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Program.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10_2_512satcvtdsintrin.h
A clang/lib/Headers/avx10_2satcvtdsintrin.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Headers/immintrin.h
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaX86.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
A clang/test/AST/ByteCode/const-base-cast.cpp
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/HLSL/vector-constructors.hlsl
M clang/test/Analysis/fread.c
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-errors.c
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64-error.c
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c
A clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c
A clang/test/CodeGen/X86/avx10_2satcvtds-builtins-errors.c
A clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c
A clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c
M clang/test/CodeGenCXX/const-base-cast.cpp
A clang/test/CodeGenHLSL/builtins/step.hlsl
M clang/test/CodeGenObjC/boxing.m
A clang/test/SemaHLSL/BuiltIns/step-errors.hlsl
M clang/test/SemaTemplate/pack-deduction.cpp
M clang/tools/CMakeLists.txt
R clang/tools/clang-format-vs/.gitignore
R clang/tools/clang-format-vs/CMakeLists.txt
R clang/tools/clang-format-vs/ClangFormat.sln
R clang/tools/clang-format-vs/ClangFormat/ClangFormat.csproj
R clang/tools/clang-format-vs/ClangFormat/ClangFormat.vsct
R clang/tools/clang-format-vs/ClangFormat/ClangFormatPackage.cs
R clang/tools/clang-format-vs/ClangFormat/GlobalSuppressions.cs
R clang/tools/clang-format-vs/ClangFormat/Guids.cs
R clang/tools/clang-format-vs/ClangFormat/PkgCmdID.cs
R clang/tools/clang-format-vs/ClangFormat/Properties/AssemblyInfo.cs
R clang/tools/clang-format-vs/ClangFormat/Resources.Designer.cs
R clang/tools/clang-format-vs/ClangFormat/Resources.resx
R clang/tools/clang-format-vs/ClangFormat/Resources/Images_32bit.bmp
R clang/tools/clang-format-vs/ClangFormat/Resources/Package.ico
R clang/tools/clang-format-vs/ClangFormat/RunningDocTableEventsDispatcher.cs
R clang/tools/clang-format-vs/ClangFormat/VSPackage.resx
R clang/tools/clang-format-vs/ClangFormat/Vsix.cs
R clang/tools/clang-format-vs/ClangFormat/license.txt
R clang/tools/clang-format-vs/ClangFormat/packages.config
R clang/tools/clang-format-vs/README.txt
R clang/tools/clang-format-vs/source.extension.vsixmanifest.in
M clang/tools/libclang/CXStoredDiagnostic.cpp
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/TableGenBackends.h
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/lib/builtins/cpu_model/aarch64.h
M compiler-rt/test/lit.common.cfg.py
M flang/include/flang/Semantics/expression.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/expression.cpp
M flang/module/__fortran_builtins.f90
M flang/module/__fortran_ieee_exceptions.f90
M flang/module/ieee_arithmetic.f90
M flang/module/iso_fortran_env.f90
M flang/runtime/edit-input.cpp
M flang/test/Driver/include-header.f90
A flang/test/Preprocessing/include-file.h
A flang/test/Preprocessing/include-line.F90
A flang/test/Semantics/elemental02.f90
M flang/test/Semantics/expr-errors06.f90
A flang/test/Semantics/kinds06.f90
M flang/test/Semantics/local-vs-global.f90
M flang/unittests/Runtime/Namelist.cpp
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/UserDocumentation.rst
M libcxx/include/__config
M libcxx/include/__stop_token/atomic_unique_lock.h
M libcxx/include/__stop_token/stop_callback.h
M libcxx/include/__stop_token/stop_source.h
M libcxx/include/__stop_token/stop_token.h
M libcxx/include/__thread/jthread.h
M libcxx/include/condition_variable
M libcxx/include/version
M libcxx/modules/std/stop_token.inc
M libcxx/modules/std/thread.inc
M libcxx/test/libcxx/experimental/fexperimental-library.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/stop_token.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/thread.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp
M libcxx/test/support/make_test_thread.h
M libcxx/utils/generate_feature_test_macro_components.py
M lld/COFF/Chunks.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
A lldb/test/API/functionalities/watchpoint/categories
M lldb/test/Shell/SymbolFile/DWARF/no_unique_address-with-bitfields.cpp
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/ProfileData/PGOCtxProfReader.h
M llvm/include/llvm/Support/FormatVariadic.h
M llvm/lib/CodeGen/InitUndef.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/ProfileData/PGOCtxProfReader.cpp
M llvm/lib/Support/FormatVariadic.cpp
M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/RISCV/RISCVCallingConv.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86InstrAVX10.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Target/X86/X86ScheduleZnver4.td
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/RISCV/arith-fp.ll
M llvm/test/Analysis/CostModel/RISCV/fp-min-max-abs.ll
M llvm/test/Analysis/CostModel/RISCV/fround.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-gather.ll
M llvm/test/Analysis/CostModel/RISCV/scalable-scatter.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll
M llvm/test/Analysis/CostModel/RISCV/splice.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
A llvm/test/CodeGen/AMDGPU/load-constant-always-uniform.ll
M llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
A llvm/test/CodeGen/DirectX/step.ll
A llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
A llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll
A llvm/test/CodeGen/Mips/Fast-ISel/underaligned-load-store.ll
A llvm/test/CodeGen/Mips/ins.ll
A llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
R llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
R llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
R llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll
A llvm/test/CodeGen/X86/avx10_2_512satcvtds-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll
A llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll
A llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-32.txt
A llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-64.txt
A llvm/test/MC/X86/avx10_2satcvtds-32-att.s
A llvm/test/MC/X86/avx10_2satcvtds-32-intel.s
A llvm/test/MC/X86/avx10_2satcvtds-64-att.s
A llvm/test/MC/X86/avx10_2satcvtds-64-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/Transforms/VectorCombine/AArch64/shrink-types.ll
M llvm/test/tools/llvm-mca/X86/Znver4/zero-idioms.s
M llvm/tools/dsymutil/Options.td
M llvm/unittests/Support/FormatVariadicTest.cpp
M llvm/unittests/Target/LoongArch/InstSizes.cpp
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/toolchain/target_flags.gni
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/asan/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/release/build_llvm_release.bat
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
M mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/28c6960e809a...8d747e19fd12
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